Subject: RE: [vhdl-200x], vital issues
From: Martyn Pollard (mjp@cadence.com)
Date: Fri Mar 14 2003 - 11:17:42 PST
It would seem that the key issue in this thread is that users want to
use Verilog Gates + SDF with a VHDL top-level testbench. The only
difference is that they don't want to use a mixed language license. Is
that a fair assessment?
If that is true, then all the major eda vendors already support
mixed-language simulation and the real issue is the pricing.
Martyn Pollard NC-Sim Product Engineering
mailto:mjp@cadence.com http://www.cadence.com
Cadence Design Systems.
270 Billerica Road, Chelmsford, MA 01824, USA
Tel; 978-262-6335 Fax; 978-262-8335
> -----Original Message-----
> From: Steve Casselman [mailto:sc@vcc.com]
> Sent: Friday, March 14, 2003 1:50 PM
> To: vhdl-200x@eda.org
> Subject: Re: [vhdl-200x], vital issues
>
>
> Just a note. I'm not suggesting that anyone get rid of Vital.
> It is (and should be) the sign-off standard. Most people can
> service 90% of their simulation/verifcation needs with a
> vastly simplified system engineered for speedy simulation.
>
> Steve
>
> > > We've just recently run into a number of integration issues with
> > > FPGA designs that functional simulation didn't catch.
> When we went
> > > looking to determine the issues, we found that VITAL simulation
> > > showed us errors in coding approaches that
>
>
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