Subject: Re: [vhdl-200x], vital issues
From: Steve Casselman (sc@vcc.com)
Date: Fri Mar 14 2003 - 10:50:29 PST
Just a note. I'm not suggesting that anyone get rid of Vital. It is (and
should be) the sign-off standard. Most people can service 90% of their
simulation/verifcation needs with a vastly simplified system engineered for
speedy simulation.
Steve
> > We've just recently run into a number of integration issues
> > with FPGA designs that functional simulation didn't catch.
> > When we went looking to determine the issues, we found that
> > VITAL simulation showed us errors in coding approaches that
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