Subject: Fw: [vhdl-200x], vital issues
From: Stephen Bailey (Stephen.Bailey@synopsys.com)
Date: Fri Mar 14 2003 - 10:30:43 PST
This bounced. I'll add Bob_Myers@raytheon.com to the post-as-well list.
-Steve
> Jim;
>
> We've just recently run into a number of integration issues
> with FPGA designs that functional simulation didn't catch.
> When we went looking to determine the issues, we found that
> VITAL simulation showed us errors in coding approaches that
> were not completely obvious (such as async reset terms, timing
> issues on bidirectional busses, etc.). After reviewing the Modelsim
> VITAL simulation waveforms, we were able to resolve a number of
> the issues we had and get the designs running in our
> integration/validation/production(?) systems. Only potential gotcha
> that we're not sure about now is the temperature aspect (running at or
> slightly
> beyond Industrial temperature ranges).
>
> Regards,
> Bob
>
> Robert J. Myers
> Technical Consultant -- PSAS HW Engineering
> Raytheon Systems Company
> 2501 W. University Drive M/S 8070
> McKinney, TX 75071
> (972) 952-4352
>
>
>
> Jim Lewis
> <Jim@synthworks.com To: Steve Casselman
<sc@vcc.com>
> > cc:
vhdl-200x@server.eda.org
> Sent by: Subject: Re: [vhdl-200x],
vital issues
> owner-vhdl-200x@ser
> ver.eda.org
>
>
> 03/14/2003 11:39 AM
>
>
>
>
>
>
> Steve Casselman wrote:
> ...snip...
> > The real question is did Vital hamstring VHDL simulation speed to the
> point
> > were engineers _have_ to use Verilog to get their work done in a timely
> > fashion?
>
> According to a paper at DVCon, Verilog gates are 4x faster than
> VHDL gates.
>
>
> > If that is the case then why not have a "gate level VHDL" format?
> This sounds great.
>
> My thought is that with economic forces at play, it sure would
> be nice for silicon vendors (and perhaps eda vendors too) if
> the VHDL format were some how compatible with the Verilog
> gate level format. This way they only need to support one
> sign-off quality gate level netlist.
>
>
> > We could call it SuperSpeed VHDL ...
> Perhaps I set my targets too low when I thought of matching
> the speed of Verilog gates. However, you sparked some ideas.
> What do we use gate level simulations for these days?
> I use static timing analysis to figure out how fast the chip
> runs. I use gate sims to find issues between RTL and gate
> (reset, ...) and as a sanity check on my timing assumptions
> made in static timing analysis. I am sure there are more.
> With some assumptions, perhaps we can even add modes to
> run gate sims without timing enabled and run considerably
> faster.
>
> Still I think we would all benefit if the base level library
> format were either based on or easily translatable
> from a Verilog library.
>
> Cheers,
> Jim
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis, www.SynthWorks.com, Expert VHDL Training
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>
>
>
>
>
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