Subject: Re: [vhdl-200x] clarifications needed
From: Stephen Bailey (Stephen.Bailey@synopsys.com)
Date: Thu Mar 06 2003 - 13:48:32 PST
Forwarding bounced message. Rick, I've added munden@acuson.com to the
post-as-well list.
> Jim,
>
> Ahhh, so thats what that is about.
>
> 1) I use VITAL for nearly everything I do and I don't do gate-level
> netlists. VITAL going away would be a major negative for me.
>
> I see nothing to make me believe that incorporating Verilog into VHDL
> would save you money on simulation licenses. The EDA vendors would just
> charge twice as much arguing (and rightly so) that the product cost
> twice as much to develop.
>
> 2) I have no problem with a standardized interface. Since I have only
> used a single vendor for mixed language simulation so far, I don't know
> if there is a problem. I am also not sure if the VHDL standard is the
> right place for this to go.
>
> Rick Munden
>
>
> Jim Lewis wrote:
> > Francoise,
> > I see there being two aspects to this.
> >
> > 1) Read Verilog Gate-level Netlists
> > Vital is not enjoying the wide support we wished for.
> > Vital is also slow compared to Verilog gate-level netlists.
> > If Vital died, silicon vendors would only need to support
> > one gate-level library format. EDA vendors would no longer
> > need to support Vital. Hence, this would be good for both.
> >
> > However, the current situation is not good for VHDL designers,
> > because to use a VHDL testbench with a Verilog gate-level
> > netlist will cost me two licenses, one for VHDL and one
> > for Verilog. Note for a Verilog designer it would only
> > cost one license.
> >
> > To benefit both users and vendors, it would be best if
> > Verilog gate-level netlists were included as part of the
> > langauge.
> >
> > 2) Standardized Verilog Interface
> > Standardize how to connect a Verilog design to VHDL.
> > This would take us away from a Vendor specific
> > implementation (which at the current time may or may not
> > be identical, but it would be nice if it were documented
> > somewhere in the standard).
> >
> > This of course should and will likely cost two licenses.
> >
> > Cheers,
> > Jim
> >
> > Francoise Martinolle wrote:
> >
> >> I noticed in the priority spreadsheet that a few people (Jim Lewis,
> >> Williams and Bishop)
> >> have voted for read and simulate Verilog netlists.
> >> I was wondering of one of them could provide a short description of
> >> this request.
> >>
> >> thanks
> >> Francoise
> >> '
> >>
> >>
> >
> >
>
>
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