Subject: Re: [vhdl-200x] clarifications needed
From: Jim Lewis (Jim@synthworks.com)
Date: Thu Mar 06 2003 - 12:37:54 PST
I see there being two aspects to this.
1) Read Verilog Gate-level Netlists
Vital is not enjoying the wide support we wished for.
Vital is also slow compared to Verilog gate-level netlists.
If Vital died, silicon vendors would only need to support
one gate-level library format. EDA vendors would no longer
need to support Vital. Hence, this would be good for both.
However, the current situation is not good for VHDL designers,
because to use a VHDL testbench with a Verilog gate-level
netlist will cost me two licenses, one for VHDL and one
for Verilog. Note for a Verilog designer it would only
cost one license.
To benefit both users and vendors, it would be best if
Verilog gate-level netlists were included as part of the
2) Standardized Verilog Interface
Standardize how to connect a Verilog design to VHDL.
This would take us away from a Vendor specific
implementation (which at the current time may or may not
be identical, but it would be nice if it were documented
somewhere in the standard).
This of course should and will likely cost two licenses.
Francoise Martinolle wrote:
> I noticed in the priority spreadsheet that a few people (Jim Lewis,
> Williams and Bishop)
> have voted for read and simulate Verilog netlists.
> I was wondering of one of them could provide a short description of this
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787
Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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