Re: [vhdl-200x], vital issues

Subject: Re: [vhdl-200x], vital issues
From: Jim Lewis (
Date: Mon Mar 17 2003 - 09:03:42 PST

Ajayharsh Varikat wrote:
> This assumes that defining a new simplified gate level standard is all
> it takes to get improved performance. I would disagree. Verilog gates
> simulate fast mainly because of the significant effort that has gone into
> accelerating them. Speeding up a new VHDL format would require similar
> optimizations, which could erode a lot of the perceived cost advantage.

Perhaps one of the design constraints should be to make the new
VHDL format similar to formats that are already accelerated
(ie: Verilog).


Jim Lewis,,  Expert VHDL Training

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