Subject: Re: [vhdl-200x] Correct Draft 2 Presentation
From: Stephen Bailey (Stephen.Bailey@synopsys.com)
Date: Tue Feb 25 2003 - 10:07:50 PST
Francoise,
> I was reviewing the slides and I have a few questions regarding the
> environment features
> which are considered for VHDL 200x:
> Can you clarify what is the intent of the enhancements connected with Verilog?
It is not possible to clarify this at this time. These are requests that we
have received and we have included them for consideration. Exactly how (or if)
these requests will be satisfied must yet be determined.
> Are you trying to standardize Verilog/VHDL mixed language use models and
> mixed language PLI? Is it supported by the scope of the PAR of vhdl200x?
This is one possibility iin a range of possible resolutions.
> . read and simulate Verilog netlists,
> . Verilog and C foreign interfaces
> . DirectC and Verilog calls
>
> The VHPI interface is currently designed to be interoperable with the VPI
> Verilog interface. In fact there is a mixed language API information which
> has been specified and published. I just don't know if this is relevant to
> the above items until I can get a better description.
>
> Can you clarify what is the intent of
> . tool specific constants
The obvious thing is for conditional analysis. You may want to key on
SynopsysDC or Synplify, for example, to determine which RTL code fragment to
use -- due to QoR impacts in coding style. Or, you may want to ensure that
debugging code is not analyzed for formal tools.
> To date, no standard specifies any tool specific constants, options.
>
> VHPI technical specification already provides the capability for some
> simulation control
> (stop, finish, reset) and to pass an arbitrary command to the tool. This is
> just some
> information in order to understand that there exists already a capability
> in the PLI
> which may make this request lower priority.
>
> . simulation control subprograms ($stop, etc...)
Yes, but that is at the C level. Users typically only access the control
language of the simulator or VHDL code itself. Obviously, whatever is done here
should be consistent with what has already been done for VHPI.
These are good questions. In some cases, it is not possible to answer
(VHDL/Verilog interfacing). In other cases, it is good to make sure we do it
properly (VHPI and sim control).
-Steve Bailey
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