Subject: [vhdl-200x] Implicit port connections for VHDL
From: Francoise Martinolle (email@example.com)
Date: Tue Feb 25 2003 - 08:23:52 PST
Another item that you may want to add to the modelling enhancements:
implicit default port/generic connections in component instantiation
This is a convenient short hand notation for connecting formal ports to
actual ports which have the same names and same type.
u1 entity lib.E(A) port map (=>);
Even you can go further and say that the port map and generic map do not need
to be specified and that the ports/generics will be connected implicitly if
declared signals and generics can be found in the same declarative scope as
the component instantiation.
u1 entity lib.E(a);
You can also mix the (=>, with port connection by name or position.
u1 entity lib.E(a) port map (b => y, c => w, =>);
u1 entity lib.E(a) port map (w, y, =>);
You can also only provide the formal if an actual of the same name and type
can found in the same scope.
signal clk, reset :STD_LOGIC;
u1 entity lib.E(a) port map (clk=>, reset=>);
The advantage is that the order of the implicit name=> port connections
does not have to match the port order of the instantiated entity contrarily
to the position connection.
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