Re: [vhdl-200x] Correct Draft 2 Presentation


Subject: Re: [vhdl-200x] Correct Draft 2 Presentation
From: Francoise Martinolle (fm@cadence.com)
Date: Tue Feb 25 2003 - 07:45:30 PST


I was reviewing the slides and I have a few questions regarding the
environment features
which are considered for VHDL 200x:
Can you clarify what is the intent of the enhancements connected with Verilog?
Are you trying to standardize Verilog/VHDL mixed language use models and
mixed language PLI? Is it supported by the scope of the PAR of vhdl200x?

  . read and simulate Verilog netlists,
  . Verilog and C foreign interfaces
  . DirectC and Verilog calls

The VHPI interface is currently designed to be interoperable with the VPI
Verilog interface. In fact there is a mixed language API information which
has been specified and published. I just don't know if this is relevant to
the above items until I can get a better description.

Can you clarify what is the intent of
  . tool specific constants
To date, no standard specifies any tool specific constants, options.

VHPI technical specification already provides the capability for some
simulation control
(stop, finish, reset) and to pass an arbitrary command to the tool. This is
just some
information in order to understand that there exists already a capability
in the PLI
which may make this request lower priority.

  . simulation control subprograms ($stop, etc...)

Francoise
        '



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