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---+ %MAKETEXT{"Welcome to the [_1] Work Group" args="<nop>%WEB%"}%

The Verilog-AMS Technical Subcommittee has been created under the auspices of <a target="_blank" href="http://www.accellera.org/">Accellera</a> with the charter to develop, update and promote analog and mixed signal extensions to the Verilog (IEEE-1364) language. This activity has resulted in the Accellera approval of the <a target="_blank" href="http://www.eda.org/verilog-ams/htmlpages/public-docs/lrm/2.3.1/VAMS-LRM-2-3-1.pdf">Verilog-AMS LRM, version 2.3.1</a>, in June 2009. This version supersedes the OVI Verilog-A LRM (from June 1996) and previous versions of the Verilog-AMS LRM. [[About][read more.....]]
---++ Working Group Information

This TWiki site is used as a repository for various documents and examples.

Administration details, confernence call information, and email distribution lists can be found on the main page at: http://www.accellera.org/apps/org/workgroup/v-ams/

To access working groups main page will require an Accellera user account.

If you work for a member company (check http://www.accellera.org/about/members <br /> for the Member company list), you can create an account here: <br /> [[http://www.accellera.org/kmembership_info/person_signup?step:int=2][http://www.accellera.org/kmembership_info/person_signup?step%3Aint=2]]

Once you have an account, you can subscribe to the Verilog-AMS Group.

If you do not work for a member company, or if you need assistance, please <br /> contact Lynn Bannister (Lynn@accellera.org) and she will be happy to set you up <br /> as an Accellera non-member.
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Topic revision: r29 - 2012-09-12 - 20:49:18 - DavidMiller
VerilogAMS