SystemVerilogDiscreteModeling < VerilogAMS

VerilogAMS Web>SystemVerilogAms>SystemVerilogDiscreteModeling (2011-05-11, KevinCameron) (raw view)EditAttach

The SV-DC (!SystemVerilog Discrete-modeling Committee) is responsible for coming up with language extensions for user-defined type on nets, which may include some levels of analog modeling.

[[http://www.eda.org/sv-dc/hm/][Mail Reflector]]

[[http://www.eda.org/svdb/view.php?id=3398][Mantiss Page - goals and proposals]]

Note: !SystemVerilog is being developed under IEEE-SA "entity only" rules.

Topic revision: r1 - 2011-05-11 - 07:04:07 - KevinCameron

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