SystemVerilogAms < VerilogAMS

VerilogAMS Web>SystemVerilogAms (2011-05-11, KevinCameron) (raw view)EditAttach

The main focus of the Verilog-AMS committee for 2011 is to merge the Verilog-AMS 2.3.1 standard with P1800-2009 !SystemVerilog. At the outset Verilog and Verilog-AMS were managed by OVI, which became Accellera. Verilog moved to the IEEE and has since spawned !SystemVerilog, but AMS stayed at Accellera [[http://www.eetimes.com/conf/date/showArticle.jhtml?articleID=12805411&kc=4005]].
   * [[SVAMS Roadmap][SystemVerilog-AMS Roadmap]]
   * [[SVAMS Section Work][SystemVerilog-AMS Section Work]]
   * [[SystemVerilogDiscreteModeling][SystemVerilog Discrete Modeling for Analog]]

Topic revision: r4 - 2011-05-11 - 06:05:53 - KevinCameron

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