OldMistakes < VerilogAMS

VerilogAMS Web>SystemVerilogAms>OldMistakes (2010-05-18, KevinCameron) (raw view)EditAttach

---++ History

The major HDLs have been around for decades, some assumptions made at the start did not hold, and some design choices have caused problems for later additions. This page is for the benefit of those who do not want to repeat the mistakes.
---+++ General
   1 Very limited support for defining power-supplies and power management.
   1 Poor interfaces into user software (C/C++).
---+++ VHDL
   1 Driver resolution is hierarchical rather than flat, which cause problems for AMS.
   1 Composite signal types are not differentiated between those representing a single physical wire and those representing busses.
   1 (Driver/Receiver) type conversion bound to ports.
   1 No plug & play for mixed signal.
   1 Incapable of representing bidirectional current flow in digital models - i.e. no pass-gate modeling.
---+++ Verilog
   1 No user-defined types, limted support for real-valued nets
---+++ Verilog-AMS
   1 Wire types (disciplines) bound to ports instead of drivers.
   1 Bad placement in connect modules (should be child/sibling of driving/receiving process) - would screw up back-annotation (see 5).
   1 Confusion in discipline/domain specification (disciplines and domains are orthoganal concepts, no need to have one in the other).
   1 No power supply hook-up method for auto-inserted connect modules.
   1 No analog/MS back-annotation methodology (have to re-netlist to add parasitics etc.)

-- Main.KevinCameron - 2010-05-18

Topic revision: r1 - 2010-05-18 - 17:57:08 - KevinCameron

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