BottomUpVerification < VerilogAMS

VerilogAMS Web>BottomUpVerification (2008-08-02, KevinCameron) (raw view)EditAttach

---+Using Verilog-AMS In Mixed-Signal Design Flows

---++Top Down Design

Most digital circuit designers are familiar with _top-down design_ where you start with abstract models of hardware and work down to transistors. Verilog-AMS supports the same kind of flow for analog and mixed signal design, allowing designers to write behavioral models of blocks which need to be fleshed out later.

---++Bottom Up Verification

Analog circuit simulation has traditionally been a source of great pain to system verification engineers. Verilog-AMS can alleviate this problem by allowing them to use checker-board techniques with optimized behavioral models, i.e. a "SPICE level" transistor circuit can be replaced with a behavioral model which has been tuned with an optimizer to match the transistor behavior and that will greatly improve simulation throughput. The same behavioral models can be used as a means to obfuscate valuable IP when sharing designs with third parties.   


-- Main.KevinCameron - 28 Mar 2008

Topic revision: r2 - 2008-08-02 - 01:00:48 - KevinCameron

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