(r5) SystemVerilogBasicCommittee < P1800

P1800 Web>SystemVerilogBasicCommittee (revision 5) (raw view)~~EditAttach~~
---+ System Verilog Basic Committee (SV-BC)

---+++ Charter

The SV-BC is the technical subcommittee of the IEEE P1800 Working Group that is tasked with maintaining and extending the design and foundational features of the System Verilog language. Currently the SV-BC is combined with the SV-EC and working on both design and testbench issues.
---+++ Email Reflector

The SV-BC uses the email reflector SV-BC@LISTSERVE.IEEENOSPAM.ORG for most of its regular communication. Subscription instructions can be found [[https://listserv.ieee.org/request/user-guide.html#How%20do%20I%20subscribe%20to%20a%20list?][here]].

Email communication prior to January 2016 is [[http://www.eda-stds.org/sv-bc/hm/][archived for reference]].
---+++ Issue Database

All IEEE 1800 Issues are tracked in the [[https://accellera.mantishub.com][Accellera Mantis Hub]].
---+++ Meeting Logistics
   * The committee is wrapping up work under the 2016 1800 PAR for editorial updates, errata and clarifications.
   * Meetings are scheduled bi-weekly on Tuesdays of even workweeks from 8am-10am PT.
   * Call Logistics are included with meeting notices emailed to the reflector.

   * Meeting Minutes
[[P1800/SvbcMinutes20160315][March 15, 2016]]

[[SvbcMinutes20160329][March 29, 2016]]

[[SvbcMinutes20160412][April 12, 2016]]

[[SvbcMinutes20160426][April 26, 2016]]

[[SvbcMinutes20160510][May 10, 2016]]

[[SvbcMinutes20160621][June 21, 2016]]

[[SvbcMinutes20160719][July 19, 2016]]

[[SvbcMinutes20160913][September 13, 2016]]

[[SvbcMinutes20161011][October 11, 2016]]

[[SvbcMinutes20161025][October 25, 2016]]

-- <span>%USERSIG{MattMaidment - 2016-03-29}%</span>

---++ Comments

<br />%COMMENT%
Topic revision: r1 - 2016-11-01 - 17:59:56 - TWikiGuest
P1800