TWiki
>
P1800 Web
>
SystemVerilogAssertionCommittee
>
SVACMeetingMinutes
>
SV-AC_Minutes_2016_10_05
(2016-10-05,
ErikSeligman
)
(raw view)
E
dit
A
ttach
Date: 2016-10-05 Time: 16.00:00 UTC (9:00 PDT) Duration: 1 hour *Agenda* * Reminder of IEEE patent policy<br /> See: http://standards.ieee.org/board/pat/pat-slideset.ppt * Minutes approval * Email ballot results * Mantis items in progress * Opens *Attendance Record* <u>Legend:</u> x = attended - = missed r = represented . = not yet a member v = valid voter (2 out of last 3 or 3/4 overall) n = not a valid voter t = chair eligible to vote only to make or break a tie Attendance re-initialized on 2016-03-09: v[.x-xxxxx---xx-] Mehbub Ali (Intel) n[.xx--x------x-] Ang Boon Chong (Intel) n[x-x-xx-x-x—x-] Shalom Bresticker (Accellera) n[.x------------] Dennis Brophy (Mentor Graphics) v[xxxxxxxxxxxxxx] Eduard Cerny (Synopsys) v[xx-xx-xxxxxxxx] Ben Cohen (Accellera) t[x-xxxxxx-xxxxx] Dmitry Korchemny (Synopsys - Chair) n[xxx-x-x-------] Manisha Kulshrestha (Mentor Graphics) v[xxxxxxxx-xx-xx] Anupam Prabhakar (Mentor Graphics) v[xxxxxxxxxxxx-x] Erik Seligman (Intel – Co-chair) n[x-x-xxxx-xx-x-] Samik Sengupta (Synopsys) |- attendance on 2016-09-21 |--- voting eligibility on 2016-09-21 *Minutes* <u>IEEE patent policy reminder</u> <u>Minutes approval</u> Erik: Move to approve the minutes from 21-Sep-2016. Ben: Second. Motion passed: 4y/0n/0a. <u>Email ballot results</u> Issue 2555 passed. Issue 3614 failed. Ben: 3614 Need to be consistent and use logical operators instead of bitwise. Erik: There are several comments about the language. Anupam: Will implement the comments and submit the updated proposal (done). Erik: Move to accept the updated proposal 3614. Ed: Second. Motion passed: 4y/0n/0a. <u>Mantis items in progress</u> 2842: Randomization of free variables in deferred assertions Anupam: Let’s postpone to the next PAR, because the solution should be rather involved. Erik: Dmitry to send an email reminder about proposal submission deadline. <u> </u> <u>Opens</u> Ben: Need to introduce syntax for local variable declaration immediately inside assertion. Erik: This is an enhancement, and we are not authorized to address it in this PAR. Ben: Need to standardize interoperability between SV and VHDL.
E
dit
|
A
ttach
|
P
rint version
|
H
istory
: r1
|
B
acklinks
|
V
iew topic
|
Ra
w
edit
|
M
ore topic actions
Topic revision: r1 - 2016-10-05 - 17:10:39 -
ErikSeligman
P1800
Log In
or
Register
P1800 Web
Create New Topic
Index
Search
Changes
Notifications
Statistics
Preferences
Webs
Main
P1076
Ballots
LCS2016_080
P10761
P1647
P16661
P1685
P1734
P1735
P1778
P1800
P1801
Sandbox
TWiki
VIP
VerilogAMS
Copyright © 2008-2026 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki?
Send feedback