SV-ACMinutes2014_11_18 < P1800

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<pre id="body"><a accesskey="j" name="start" id="start"></a>Minutes from SV-AC Committee Meeting <pre>
Date:     2014-11-18
Time:     17:00 UTC (9:00 PST)
Duration:  1 hour

Agenda
------

- Reminder of IEEE patent policy.
See: http://standards.ieee.org/board/pat/pat-slideset.ppt

- Elaborating recommendations for the next P1800 PAR.

- Opens


Attendance Record:
------------------
         Legend:
                 x = attended
                 - = missed
                 r = represented
                 . = not yet a member
                 v = valid voter (2 out of last 3 or 3/4 overall)
                 n = not a valid voter
                 t = chair eligible to vote only to make or break a tie

Attendance re-initialized on 2014-11-18:

  v[x] Shalom Bresticker (Intel)
  v[x] Dennis Brophy (Mentor Graphics)
  v[x] Eduard Cerny (Synopsys)
  v[x] Ben Cohen
  v[x] John Havlicek (Cadence)
  v[x] Tapan Kapoor (Cadence)
 t[x] Dmitry Korchemny (Intel - Chair)
  v[x] Scott Little (Intel)
  v[x] Anupam Prabhakar (Mentor Graphics)
  v[x] Erik Seligman (Intel)
  v[x] Samik Sengupta (Synopsys)
    |- attendance on 2014-11-18
  |--- voting eligibility on 2014-11-18



Minutes
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1.  IEEE patent policy reminder

2. Elaborating recommendations for the next P1800 PAR

Update (Dmitry)
Next meeting of IEEE P1800 WG will take place at DVCon'2015 and it will be decided regarding the next steps. Towards this meeting the subcommittees should elaborate their recommendations regarding the next PAR. The general opinion at the last IEEE P1800 WG meeting was to have a "quiet" PAR with minimal number of changes. Main exceptions: work required to merge Verilog-AMS with SystemVerilog (mostly belongs to SV-DC subcommittee), and work required to support the standardization of UVM (P1800.2; mostly belongs to SV-EC subcommittee).
Ben:
Suggesting the following enhancements for the next PAR
*        Make drivers of inout ports accessible  (Mantis 3478). Probably belongs to SV-BC.
*        Allow concurrent assertions in classes
*        Allow local variables in time windows
John: Having concurrent assertions in classes is important.
Dmitry: This may be related to UVM as this will allow to use checkers in UVM.
John, Ed: This enhancement is huge.
Dmitry: It might make sense to start working on it during the next PAR, but issue only in the PAR following it.
Ben: The proposal is well-defined.
John: Local variables in time windows should be a feasible enhancement
Dmitry: Inout port drivers enhancement is related to the problem of automatic inference of assert statement for FV. E.g., assertions specified on inputs should be treated as assumptions, other assertions as assertions. More refinement for inout ports.
Everybody agrees to include errata and clarifications to the next PAR.
Dmitry suggested to develop standard packages. One defining constants (magic numbers) in the LRM (such as Lock/Unlcok for $assert_control), and the other to contain standard properties (e.g., equivalents of next_event family in PSL) and include them as annexes.
Ben and John supported the idea.
Dennis: Should these annexes be normative or informative?
Dmitry: Eventually they should be normative, but in the next PAR they may be released as informative.
Dmitry will send the list of discussed issues to the subcommittee, and the subcommittee members will provide their feedback for each issue: important /nice to have/ not important.
3. Opens
None
Next meeting: Monday, 2014-12-01 - 16:30 UTC (8:30 am PST)</pre> </pre>
Topic revision: r1 - 2014-11-21 - 17:56:59 - ErikSeligman
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