SV-ACEffortEstimateStatementToP1800WorkingGroup < P1800

P1800 Web>SystemVerilogAssertionCommittee>SV-ACEffortEstimateStatementToP1800WorkingGroup (2010-05-28, ErikSeligman) (raw view)EditAttach

Below are SV-AC effort estimates for the top priority SV-AC issues. The statement was unanimously approved by voice vote at the SV-AC meeting 2010&ndash;05&ndash;24.

The SV-AC determined effort estimates for the twelve categories as follows:

 1. AMS assertions (4 months)

 2. Checker usability (4 months)

 3. Assertion system functions (1.5 months)

 4. Inference (0.5 month)

 5. Sampling (2 month)

 6. Local variables (1.5 months)

 7. Scoping (6 months)

 8. Type system (4 months)

 9. Covergroups (4 months)

10. Formal Semantics (1 month)

11. Vacuity (0.5 month)

12. Temporal logic (1 month)

This amounts to 30 months of development effort. We believe that 2 months also need to be allocated for errata and minor issues. The assumption is that the committee can work on 2 major items in parallel. Therefore, the 17 months remaining in the PAR are enough provided we can begin development work soon. However, the committee understands that these estimates are approximate and the difficulty of resolving some items is not well understood. The committee may decide not to resolve some items under a category.

Topic revision: r1 - 2010-05-28 - 15:23:10 - ErikSeligman

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