June 25 2007 - P1778 workgroup Meeting Minutes

• Workgroup: P1778 - Esterel v7 language standardization
• Location: Teleconference (see Next Meeting to connect)
• Date: June 25 2007
• Chair: Gerard Berry
• Vice Chair: Stephen Edwards
• Secretary: Sylvan Dissoubray

Attendance

• See Attendance Record for meetings participation history

Agenda

Process

• Start: Chair declares the meeting open at 5:10
• Agenda: The agenda is approved by participants
• Minutes: No objections about last meeting minutes -- they are approved
• Patents: No new item . The page IEEE Patent Policy holds the call for patent, and workgroup status.

Technical topics

Brief summary of discussion, pros and cons, and conclusions

= About data chapter.

New version on data will be included. A pdf version will be uploaded.

Still some comments already discussed to be included.

Make version of the files and dates clearer, included in file name.

Current discussion is on page Esterel v7 Tex LRM Arithmetic and Bitvectors chapter.

• Many errors in the chapter found by LZ and corrected by GB.

• Proposal to reduce number of bin2u and u2bin for discussion today.

• New points on arithmetics from Eric Badi:
  • Functional module calls and generalized mux (i.e. mux with multiple entries, more readable and more efficient than a cascade of mux's).
  • See notes in the arithmetics discussion page.

• The extended map proposal is discussed and receives general positive feedback.

• Discussion about static sizes or computed sizes for arrays.
  • Compile time evaluable
  • Expressions depending on loop iterator indexes. Compile time expansion (e.g. triangular arrays)
  • Dynamic expressions
  • Host constants (also difficult for type checking)

• Differences between software and hardware about host functions
  • Aim for the best integration with host constants, functions which are more used for software applications. Integration of a foreign type should be made easier in the language, in particular the use of host operators: +, * ... But this will make formal verification difficult.

• Restriction on arrays of arrays in Verilog generation. Arrays of arrays were previously forbidden in Verilog generation. They are now allowed, under the condition that they are inside the design, not at the boundary, due to Verilog limitation. Notice that there are no restriction on arrays of arrays in SystemVerilog.

• Genericity
  • Esterel genericity is not standard. Advice seeked from Caml group genericity before presentation to workgroup. Chapter genericity is important and requires careful discussion (not the next chapter discussed).

• Naming
  • Using underscore a__b in names is currently forbidden. It should be allowed.
  • Underline at the start _a is also forbidden, because it is used in generated C code to protect generated names. Should it be allowed?
  • Od123_456 is allowed, why not in normal numbers: 123_456?

• Interfaces
  • Need to distinguish a signal in an interface from a module signal, which are different objects in the language. It is decided to say "interface signal" for a signal in an interface.
  • Should we introduce a notion of interface with no direction, which would be useful for an interface that is used in a local signal declaration: "signal extends intf in" or "signal port p : intf in", where signal directions are ignored.

• Registered signals
  • Should we replace "reg" with "next" in the declaration of registered signals? "reg" is always used in Verilog, with ambiguous meaning (does not declare a register). Should we speak of "next signals" instead of "registered signals"? In comparison, mem signals also generate a register.
  • Why repeating, "next" in registered signals emissions? In comparison, "temp" is not repeated.

Next Chapter for discussion

• Signals will be the next chapter submitted for discussion.

• In particular important discussion about default for signals temp or not, full or value only.
  • Proposal to switch to explicit mem, reg, and full (making temp and value only the default)
  • NB migrating can be helped by the compiler itself, by going through a first step of making all defaults explicitely written.

• Difference also between persistency and memorization (being accessible always can be true even if memory is somewhere else).

• Signal in modules is not the same as a declaration in interface (documented in different chapter). Saying interface signals would remove ambiguities.

• NB: directionalities in interfaces and mirorring saves compared with System Verilog. Should we also allow for directionless interfaces ?

Motions and actions items with name and due date

• Check all access to wiki
• MP will distribute data chapter in IEEE format
• Currently data and arithmetics chapter are cooling down: all send an email about points they raised to be sure they are addressed
• Read signals and interface chapters for next. GB will put new proposal on wiki.
• KS will explain how it works in Quartz
• In sequence or in parallel, read genericity chapter to keep difficulties in mind.

Adjournment and Next meeting date

Next meeting proposal: Thursday 23 August Time to be confirmed later

Meeting is closed at 6:50 PM.