LCS2016_043_history < P1076

P1076 Web>VHDL2017>LCS2016_043>LCS2016_043_history (2017-07-16, JimLewis) (raw view)EditAttach
---+ Language Change Specification for API and Attributes for PSL

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| <sticky><b>LCS Number:</b></sticky> | LCS-2016-043 |
| <sticky><b>Version:</b>   </sticky> | 2 {16-Jan-2017} |
| <sticky><b>Date:</b>      </sticky> | 16-Jan-2017  |
| <sticky><b>Status:</b>    </sticky> | Voting |
| <sticky><b>Author:</b>    </sticky> | Jim Lewis |
| <sticky><b>Email:</b>     </sticky> | [[Main.JimLewis]] |
| <sticky><b>Source Doc:</b></sticky> | [[PslAttributes][API and Attributes for PSL]] |
| <sticky><b>More Doc:</b></sticky> | [[LCS2016_043_history][history]] |
| <sticky><b>Summary:</b>   </sticky> | API and Attributes for PSL |

---+++ Voting Results: Cast your votes here

Yes:

   1 %USERSIG{JimLewis - 2017-01-16}% ver 2
   1 %USERSIG{PatrickLehmann - 2016-12-31}% - ver 1
   1 %USERSIG{TorstenMeissner - 2017-01-01}% - ver 2
   1 %USERSIG{PeterFlake - 2017-03-09}% - ver 2

No:

Abstain:
   1 %USERSIG{MartinZabel - 2017-01-23}% Any version - I have no experience with PSL.
   1 %USERSIG{LievenLemiengre - 2017-01-27}%
   1 %USERSIG{HendrikEeckhaut - 2017-01-27}% ver 2
   1 %USERSIG{YannGuidon - 2017-02-07}%
   1 %USERSIG{BrentHahoe - 2017-02-16}% Version 2 - Abstain due to lack of personal time for review.
   1 %USERSIG{MartinThompson- 2017-02-17}% Version 2 - I have never used PSL so far so cannot comment.

---++ Revision Notes

Revision 2:  
   * To 'Signal attribute adds text about assume and restrict directives.

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<sticky>

 
---++ Reviewing Notes
This LCS only intends to implement the basic features of 
the proposal.  
If an extended or advanced feature of the proposal is
to be implemented, it should be implemented by a separate
LCS and voted on separately.



---++ Comments 



The defined attributes would be very helpful. They could be useful in testbenches to control the random test stimuli based on the state of PSL directives. I think the P&#39;event attribute is more useful, because it&#39;s a function which can be used more flexible in VHDL code. What does complete mean for an PSL assertion? It has reached the end of the underlying property with fail or good state? So after checking the P&#39;event tribute, I would have to use the P&#39;signal attribute to get the concrete completion state of the assertion, I assume.

-- %BUBBLESIG{TorstenMeissner - 2017-01-01}%


I would add following sentence to the Result section of P&#39;SIGNAL. After &#34;A PSL cover value of TRUE indicates that is was satisfied during a given cycle.&#34; : &#34;Assume and restrict directives are treated like assert. Fairness directives are not supported.&#34;

-- %BUBBLESIG{TorstenMeissner - 2017-01-09}%


Done in version 2

-- %BUBBLESIG{JimLewis - 2017-01-16}%


@TODO  2-Mar meeting
Does PSL update on postponed cycles?
If yes, need to note this in P&#39;Signal and processes using P&#39;Signal must not trigger any delta cycles

-- %BUBBLESIG{JimLewis - 2017-03-02}%
%COMMENT%</sticky>

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Topic revision: r1 - 2017-07-16 - 12:30:15 - JimLewis
P1076