Embedded FSM Language

Proposal Details

Authors Patrick Lehmann
Date Proposed 2017-04-02
Last Updated 2017-04-02
Focus simulation and synthesis
LCS TBD

Summary

State machine are currently written in a 1-, 2- or 3 process pattern using regular VHDL process statements. It proposal presents a concurrent statement that describes a state machine with various extra features which are hard to implement in normal process based FSMs.

Current Situation

There are three accepted VHDL coding pattern to describe a state machine in VHDL:
  1. 1 process pattern
  2. 2 process pattern
  3. 3 process pattern

Requirement

The new statemachine statement shall support the following features:
  • Single clocked
  • Synchronous and asynchronous reset
  • Required default assignments (no latches)
  • Clear transitions on goto
  • Entry and exit handlers
  • Selectable encoding via attribute
  • Supports Mealy and Moore type
  • Supports init (FPGA) and reset state (both)

Planned features

  • Sub state machines
  • Virtual states
  • State machine to state machine communication

Use Cases

Add some use cases.

Implementation details

New reserved words:

  • statemachine
  • state
  • entry
  • goto

Code Examples

statemachine myFSM is
  configuration (
    Clock =>     clk,
    SyncReset => rst,
    -- ASyncReset => rst_a
    InitialState => IDLE,
    Reset state => IDLE
  );
  default (
    LeaveIdle => ‘0’,
    Working => ‘0’,
    ErrorRaised => ‘0’
  );
  state IDLE is
    goto WORKING;
    on exit to (all)
      LeaveIdle <= ‘1’;
    end on exit;
  end state;

  state WORKINK is
    Working <= ‘1’;
    goto ERROR when (err = ‘1’);
  end state;

  state ERROR is
    on entry from (WORKING)
      ErrorRaised <= ‘1’;
    end on entry;
  end state;
end statemachine;

Arguments FOR

  • Clean syntax
  • Lower complexity for big FSMs compared to process pattern
  • No pattern matching in VHDL tools to find FSMs

Arguments AGAINST

  • 4 new reserved words

General Comments

Supporters

  • Patrick Lehmann - 2017-04-02
  • Add your signature here to indicate your support for the proposal


This topic: P1076 > WebHome > VHDLProposals > FSMLanguage
Topic revision: r2 - 2017-04-02 - 22:11:18 - PatrickLehmann
 
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