(r30) ActiveIRTwiki < P1076/Ballots

P1076/Ballots Web>IssueScreening>ActiveIRTwiki (revision 30) (raw view)~~EditAttach~~
---+ Active IR List from VHDL-2008

Revised: -- Main.JimLewis - 2014-06-22

---++ IRs accepted for consideration in VHDL-201X

These items have been forwarded from ISAC requests to be considered for the next language revision.
| *IR #*  | *BugZ#*  | *Link to Proposal*  | *Problem to Solve*  | *Description*  | *Notes*  |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2109.txt][2109]]  | - | Enhance  | Interface / Com  | Semaphore with protected types  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2033.txt][2033]]  | - | Enhance  | | Incremental operator and auto subtype boundary wrap  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2108.txt][2108]]  | - | [[WaitLevel]]  | Testbench Sync  | Level sensitive check - A "wait" that checks condition before stopping  | Referred to in: [[WaitRepeat][Wait with a repeat count]] |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2003.txt][2003]]  | - | [[MultiCyclePath]]  | | Specification of multi-cycle paths to synthesis tool w/o creating registers.<br />[[Main.JimLewis][Jim Lewis]]: During meeting how in general specify this and perhaps capture false paths as well and simulate them  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2113.txt][2113]]  | - | [[ReadRom]]  | General  | Init ROM / Array data structure with a file - syntax or library (types + std subprogs)  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2119.txt][2119]]  | - | [[DeferredSharedVariables]]  | Interface / Com  | Can't declare a protected type and object of that type in a single package  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2121.txt][2121]]  | [[https://bugzilla.mentor.com/show_bug.cgi?id=275][275]] | [[Partiallyconnectedvectorsonportmap][Partially Connected Vectors in Port Map]]  | General  | Allow for vectors to have assigns and opens in the port map  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2125.txt][2125]]  | - | [[StdulogicResolution][Std_ulogic, Resolved, and '-']]  | Interface / Com  | Resolution of '-' and 'Z' is 'X", ok for RTL, but bad for testbenches?  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2007.txt][2007]]  | - | [[BidirectionalConnections]]  | | VHDL needs to be enhanced to allow the modeling of switches. (forward to VHDL-AMS?)  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2009.txt][2009]]  | - | [[ConditionalCompilation]]  | | New std package, containing tool and vendor identification information<br />Needs to be considered in conjunction with conditional compilation. May need to be precompiler directives  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2011.txt][2011]]  | - | [[ComponentDerivedFromEntity]]  | | Syntax that creates a component declaration from an entity decalaration and puts it into a specified package  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2012.txt][2012]]  | - | [[UniqueCondition]]  | | Wants to remove the priority from if-elsif-elsif structures under some conditions. Proposes: "if elsor elsor".  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2021.txt][2021]]  | - | [[DynamicRewiring]]  | | Dynamic hardware construct  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2025.txt][2025]]  | | [[ConditionalCompilation]]  | | "Generate" for sequential code (c.f. ConditionalCompilation)  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2106.txt][2106]] | | [[ConditionalCompilation]] | | Desire preprocessor (macro/ifdef) support in VHDL | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2034.txt][2034]]  | - | [[ClockedShorthand]]  | | Introduce history attribute on signals to auto infer registers  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2035.txt][2035]]  | - | [[ClockedShorthand]]  | | new function "stages" automates pipelining  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2041.txt][2041]] | | [[Partiallyconnectedvectorsonportmap]] | | Allow composite port subelements to be left open. | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2060.txt][2060]] | | [[TruthTable][Truth Tables]] | | Include truth table for multi-input/multi-output logic. | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2072.txt][2072]] | | [[RangeOperations][Operations on Ranges]] | | Allow static operations on "ranges" | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2089.txt][2089]] | | [[BlockInterfaces][Interfaces]] | Interfaces | Directional records | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2100.txt][2100]] | | [[ProtectedTypeOperators][Operators Overloading for Protected Types]] | | <p>Operator overloading for protected type methods</p> | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2076.txt][2076]] | | [[RecordMemberAttribute][Record Member Attribute]] | | A member attribute for records. | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2065.txt][2065]] | | [[RelaxedOthersAggregate][Relaxed Others Aggregate]] | | OTHERS in aggregates too restrictive | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2067.txt][2067]] | | [[BlockInterfaces][Interfaces]] | | Enhancement: Logical link interface abstraction | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2103.txt][2103]] | | [[DynamicRewiring]] | | Dynamic/run-time creation and destruction of components and connectivity | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2130.txt][2130]] | [[https://bugzilla.mentor.com/show_bug.cgi?id=239][239]] | [[OverloadAssignment][Overload Assignment]] | | Ability to overload the assignment operator := would be useful | Concerns |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2132.txt][2132]] | [[https://bugzilla.mentor.com/show_bug.cgi?id=240][240]] | [[FunctionKnowsVectorSize]] | | Method to allow functions that return arrays to have knowledge of the target attributes | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=295][295]] | [[RemoveConfigurationLibraryRequirement]] | | Allow configurations for entities not in the same library | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=294][294]] | [[ForcingOutports][Force and Out Ports]] | | Force of an out port using mode is improperly defined | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=293][293]] | [[AlternatePathName][Alternate Path Name]] | | Issue with path_name and instance_name wrt VHDL-2008 generate labels | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=292][292]] | [[ConfigureDirectInstantiation]] | | Configure Architecture of Direct Entity Instantiation | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=291][291]] | [[CompositesProtectedTypes][Composites of Protected Types]] | | Allow composites to have elements that are protected types. | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=290][290]] | [[MethodParametersAccessTypes][Method Parameters that are Access Types]] | | <p> </p> <p>Allow method parameters to be of an access type.</p> | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=289][289]] | [[Fix2008ContextClause]] | | Context declaration requirements are not uniform | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=288][288]] | [[NewRulesBitLiterals][New Bit Literal Rules]] | | Bit string literals not correctly defined | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=287][287]] | [[ProcessAllIncudesAllReachableSubprograms][Process all and global signals]] | | process(all) non-parameter signal read error should be errorenous | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=286][286]] | [[Fix2008LRM7321]] | | incremental binding example is illegal | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=285][285]] | [[WriteBoolean][Boolean TEXTIO Write]] | | textio write[line,boolean...] is not backward compatible across language versions | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=284][284]] | [[http://www.eda.org/twiki/bin/view.cgi/P1076/FixedFloatUpdates][Fixed + Float Pkg updates]] | | Sizing rules for fixed point reciprocal are wrong | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=282][282]] | [[PackageNameCase][Package Name Capitalization]] | | Give IEEE package names consistency capitalization | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=281][281]] | [[http://www.eda.org/twiki/bin/view.cgi/P1076/FixedFloatUpdates][Fixed + Float Pkg updates]] | | Discrepancies between float_generic_pkg.vhdl and float_generic_pkg-body.vhdl (unresolved_unsigned vs unsigned) | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=278][278]] [[https://bugzilla.mentor.com/show_bug.cgi?id=280][280]] | [[PrecedenceUnaryLogical][Precedence of Unary Logical Operations]] | | Clarify precedence of logic reduction operators | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=277][277]] | [[TextioBvSlv][Read of bit_vector vs. std_ulogic_vector]] | | Read of bit_vector and std_ulogic_vector differ slightly. | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=276][276]] | [[StopReadOnTrailingUnderscore]] | | '_' at the end of hex and octal reads | |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=259][259]] | [[NoOverridingPredefinedAttributes][User-Defined Attributes May Not Redefine Predefined Attributes]] | | attribute declaration with same designator as a predefined attribute | |
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---++ IRs for 1076.6
| *IR #*  | *BugZ#*  | *Status*  | *Responsible*  | *Description*  | *Notes*  |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2114.txt][2114]]  | - | | | 1076.6-2004 section 8.6.5 Slice names is too restrictive.  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2066.txt][2066]] | | | | Support multidimensional arrays in IEEE Std 1076.6-2004 | |

---++ IRs Rejected
| *IR #* | *BugZ#* | *Status* | *Date* | *Description* | *Notes* |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2027.txt][2027]] | - | Reject | [[2013_MeetingAug29][Aug 29, 2013]] | When loop index is static, drivers are created for each element of array | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2131.txt][2131]] | [[https://bugzilla.mentor.com/show_bug.cgi?id=233][233]] | Reject | [[http://www.eda.org/vhdl-200x/hm/2032.html][Email]] | Vhpi_user.h requires enum types contents update/completion | Information available in parent. |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2026.txt][2026]]  | - | Reject | [[http://www.eda.org/twiki/bin/view.cgi/P1076/2014_MeetingAugust7][Aug 7, 2014]] | Upward propagating parameters  | VHDL-2008 introduces external names to constants (including generics) that addresses this request. Hence, out generics would be a redundant feature |
| | [[https://bugzilla.mentor.com/show_bug.cgi?id=283][283]] | Reject  | [[http://www.eda.org/twiki/bin/view.cgi/P1076/2014_MeetingMay1][May 1, 2014]] | ?/= function in float_generic_pkg can give wrong answer | Resolved as Invalid  |

---++ IRs Completed in VHDL-2008 by either Accellera VHDL WG or VASG
| *IR #*  | *BugZ#*  | *Status*  | *Responsible*  | *Description*  | *Notes*  |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2005.txt][2005]]  | - | Done  | | sla operator behavior does not match typical hardware behavior<br />Base language did not change. Instead it is fixed in packages. It is overloaded in numeric_bit_unsigned for bit vector. For std_logic_vector is not be defined unless numeric_std_unsigned is included.  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2117.txt][2117]]  | - | Done  | | Block comment is not there in vhdl  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2118.txt][2118]]  | - | Done, Duplicate  | | Typo in 9.2 Note 2  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2006.txt][2006]]  | - | Done  | | "else" in "if generate"?  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2014.txt][2014]]  | - | Done  | | Allowance of the keyword "all" in place of a sensitivity list is desirable  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2015.txt][2015]]  | - | Done  | | Generics should be able to incorporate other generics  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2016.txt][2016]]  | - | Done, Duplicate  | | Allowance of the keyword "all" in place of a sensitivity list is desirable  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2017.txt][2017]]  | - | Done, Duplicate  | | Generics should be able to incorporate other generics  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2019.txt][2019]]  | - | Done  | | Reading outputs from within architecture  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2022.txt][2022]]  | - | Done  | | Elements of constant composite to be locally static  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2024.txt][2024]]  | - | Done  | | VHDL needs encryption support  | <p> </p> |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2046.txt][2046]] | | Done | | AKA Type Generics: Type independent ports and subprogram parameters | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2088.txt][2088]] | | Done | | Formatted I/O | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2054.txt][2054]] | | Superceded | | Individual assoc. rules for array formal are not valid | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2063.txt][2063]] | ? [[https://bugzilla.mentor.com/show_bug.cgi?id=42][42]] | Forwarded | | Unconstrained array formals should not get subtype from actuals | |

---++ IRs Completed in VHDL-2008 by ISAC
| *IR #*  | *BugZ#*  | *Description*  | *Notes*  |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR1000.txt][1000]]  | | Accumulated typographical and terminology errors.  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR1044.txt][1044]]  | | Definition of 'HIGH and 'LOW in a null range  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR1070.txt][1070]]  | | VPI Issue 14 -- Prefixes in USE clauses  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2000.txt][2000]]  | | Where may/must deferred constant declaration appear  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2001.txt][2001]]  | | Resize not working in numeric_std.vhd (1076.3  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2002.txt][2002]]  | | Resize(R.2) function in numeric_std.vhd does improper array length check  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2004.txt][2004]]  | | Definition of SLA doesn't make sense  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2008.txt][2008]]  | | Source value of undriven, non-sourced INOUT, OUT or BUFFER port  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2010.txt][2010]]  | | The description of type/subtype relationship could be better  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2013.txt][2013]]  | | Exact subtype "matching" for port associations  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2018.txt][2018]]  | | Variable IN parameter should be no different than constant  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2020.txt][2020]]  | | Keyword REPORT is over-used  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2023.txt][2023]]  | | Add predefined array types for integer, boolean, real and time  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2028.txt][2028]]  | | Clarify simulation cycle.  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2029.txt][2029]]  | | Non-relevant words and paragraph.  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2030.txt][2030]]  | | What signature does a method have  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2031.txt][2031]]  | | "mod" function needed for TIME  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2032.txt][2032]] [[http://www.eda.org/isac/IRs-VHDL-2002/IR2032.1.txt][2032.1]]  | | Function "now" is not pure  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2036.txt][2036]]  | | protected_type_declarative_item includes subprogram_specification  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2037.txt][2037]]  | | Typo wrt now in the index  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2038.txt][2038]]  | | Minor semantic errors  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2039.txt][2039]]  | | Minor typos  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2040.txt][2040]]  | | Problems with OTHERS in aggregates  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2042.txt][2042]]  | | Architecture as a block causes problems  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2043.txt][2043]]  | | Numeric VALUE attribute parameter can't have sign  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2044.txt][2044]]  | | Deprecation of linkage ports affects boundary scan description language  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2045.txt][2045]]  | | Add the ability to comment an entire block of code  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2047.txt][2047]]  | | Backslash in extended identifiers  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2048.txt][2048]]  | | Miscellaneous errors  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2049.txt][2049]]  | | Circular definition of an event on a signal  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2050.txt][2050]]  | | Definition of S'Last_Value was apparently broken in 1993  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2051.txt][2051]]  | | Path_name and instance_name do not allow for protected types  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2052.txt][2052]]  | | Path_name and instance_name don't deal with operator symbols  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2053.txt][2053]]  | | Minor Typos in VHDL 2002 part 2  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2055.txt][2055]]  | | Prohibition on assignment of protected types not normative  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2056.txt][2056]]  | | Can an attribute name that denotes a function be used where a name is required?  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2057.txt][2057]]  | | Access-typed parameters to predefined "=" and "/="  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2058.txt][2058]]  | | Does USE of type name make operators and literals visible?  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2059.txt][2059]]  | | Upper/lower case character mapping is not clear  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2061.txt][2061]]  | | Default actions on severity flags is different between simulators  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2062.txt][2062]]  | | Range staticness  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2064.txt][2064]]  | | Type conversion of unconstrained output in a port map  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2068.txt][2068]]  | | Entity instantiation with space before the entity name  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2069.txt][2069]]  | | Visibility of generics in block configurations  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2070.txt][2070]]  | | Support for floating point denormal numbers  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2071.txt][2071]]  | | Indexed name in case expression  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2073.txt][2073]]  | | Index constraints and discrete range conversions from universal_integer  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2074.txt][2074]]  | | Problem with direct/select visibility in formal part  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2075.txt][2075]]  | | Arrays with numeric and enumeration index types are not closely related  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2077.txt][2077]]  | | Incorrect wording on some language constructs  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2078.txt][2078]]  | | Allow attribute declaration/specification in package body  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2079.txt][2079]]  | | Is TIME a locally static type?  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2080.txt][2080]]  | | Case expression should include parenthesized expression  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2081.txt][2081]]  | | The term ancestor is used where parent is meant  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2082.txt][2082]]  | | Elaboration of unconstrained interface objects  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2083.txt][2083]]  | | Generate index specification should be of same subtype as generate parameter  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2084.txt][2084]]  | | A record "element" is not called a "field"  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2085.txt][2085]]  | | What happens when a parameter of mode out is not assigned in a procedure?  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2086.txt][2086]]  | | Incorrect description of type mark in disconnection specification  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2087.txt][2087]]  | | Ambiguous rule for type of an alias declaration  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2090.txt][2090]]  | | Signature in alias declaration for "not" wrong  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2091.txt][2091]]  | | Translation between std_logic_vector based types and std_ulogic_vector  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2092.txt][2092]]  | | Type conversions don't allow for null arrays  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2093.txt][2093]]  | | Static type conversions and qualified expressions  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2094.txt][2094]]  | | Attribute specifications of overloaded subprograms is limited  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2095.txt][2095]]  | | What is the entity class of an enumeration literal?  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2096.txt][2096]]  | | Error is ambiguous  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2097.txt][2097]]  | | Operations with Array aggregates  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2098.txt][2098]]  | | Ambiguity in definition of T'VAL for Physical types  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2099.txt][2099]]  | | Alias declarations introduce homographs  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2101.txt][2101]]  | | Type conversion - implicit refers to section 8.1.2 which doesn't exist  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2104.txt][2104]]  | | Using a configuration to leave a design unbound  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2105.txt][2105]]  | | Can't declare an alias of a character literal without using expanded name  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2107.txt][2107]]  | | Editorial process dropped a \ from extended identifier example  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2111.txt][2111]]  | | Unknown term used: selector  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2115.txt][2115]]  | | Binding specification should be binding indication  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2116.txt][2116]]  | | What is the direction of std_logic_vector & '0'  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2120.txt][2120]]  | | How to access objects in higher level nested protected type  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2122.txt][2122]]  | | Protected method has implied object parameter?  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2123.txt][2123]]  | | Process resumption and callbacks  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2124.txt][2124]]  | | Ordering of process execution and callbacks  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2126.txt][2126]]  | | Concatenation ambiguity  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2127.txt][2127]]  | | Possible LRM interpretation pitfall related to the predefined STANDARD package  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2128.txt][2128]]  | | Shared Variable declarations in generate?  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2129.txt][2129]]  | | Bad requirements to check exprs with access type sub exprs  | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2110.txt][2110]] | | Implicit subtype conversions not defined | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2112.txt][2112]] | | Can attributes be applied to a signal on the entity within the architecture for that entity? | |
| [[http://www.eda.org/isac/IRs-VHDL-2002/IR2102.txt][2102]] | | Duplicate: Typo in Section 3.2.1. Example | |

[[http://www.eda.org/isac/IRs-VHDL-2002/activeIRs.txt][Original Active IR list dated 18 June 2008]]
Topic revision: r1 - 2016-09-27 - 10:47:26 - TWikiGuest
P1076/Ballots