2020_0827_Meeting < P1076

P1076 Web>Vhdl202X_MeetingMinutes>2020_0827_Meeting (2020-08-27, JimLewis) (raw view)EditAttach

---+ P1076 Minutes from August 27, 2020
---++ Attendees
   * Peter Flake, Unai Martinez-Corral, Lieven, Jim
---++ Meeting Discussion
   * DPI
      * 
   * LaTex 
      * 

   * Issues of VHDL-2008 aggregates wrt LHS?
      * Goal:

<pre>
(Cout, Sum8) &lt;= ('0' & A8) & B8 ;

-- All OK:
type slv_2d is array (natural range <>) of std_logic_vector;

 constant aggregate1  : std_logic_vector := ('1', "1010", '0');
 constant aggregate2  : std_logic_vector := ('1', ('1', ('0', ('1', '0'))));
 constant aggregate22 : std_logic_vector := ('1', ('1', ('0', "10")));
 constant aggregate3  : std_logic_vector := (((('1', '1'), '0'), '1'), '0');
 constant aggregate4  : slv_2d           := ((((('1'), '1'), '0'), '1'), ('0', '1', '0', '1'));
</pre>
-- Problematic with GHDL:
<pre>type my_new_type is array(natural range &lt;&gt;) of std_logic_vector(31 downto 0);

-- Then I declare a constant of that new type 
constant constant_of_my_new_type : my_new_type (0 to 7) := ((others=&gt;(others =&gt; '0')));

signal signal_of_my_new_type 		: my_new_type (0 to 7);

begin

process(clk_i)
begin
	
	-- if Reset low then signal_of_my_new_type = constant_of_my_new_type
	-- else, signal_of_my_new_type is filled with one at the next clock rising edge

	if n_rst_i = '0' then
		signal_of_my_new_type &lt;= constant_of_my_new_type;
	elsif rising_edge(clk_i) then
		signal_of_my_new_type &lt;= ((others=&gt;(others =&gt; '1')));
	end if;</pre>

---++ Next Meeting

10 September 2020, 11 am Pacific *Daylight* Time (GMT-7)

---++ Comments

%COMMENT%

Topic revision: r1 - 2020-08-27 - 19:48:02 - JimLewis

P1076