2016_MeetingMay5 < P1076

P1076 Web>Vhdl2019MeetingMinutes>2016_MeetingMay5 (2020-02-17, JimLewis) (raw view)EditAttach
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---+!! P1076 May 5, 2016 Meeting Minutes
---++!! Attendees:

   * Brent Hayhoe, Rob Gaddi, Jim Lewis, Ernst Christen, Jing Pang
---++!! Agenda:

%TOC%

---++ Meeting Discussion
   * Review [[PrivateDocuments]] file: _summary_vhdl_requirements_priority.xlsx
   * Restart at line 75
   * 64: Wait Level
      * Does LRM allow expressions on in mode signal parameters? It does work for ports (6.5.6.3)?
      * If it is not the case, it seems the simplest path is to make it so.
      * Does it matter if it is a concurrent or sequential subprogram call?
   * 65: Named Package Bodies
      * <span data-mce-mark="1" style="background-color: transparent;">If not, we would could use an abstract package to implement this.</span>
      * <span data-mce-mark="1" style="background-color: transparent;">Do we need the capabiltiy to use both packages at the same time?</span>
         * If this is a limited use case, could pass two abstract packages to the entity.
   * 66: Unions / Variant Records
      * Need for higher functionalilty in functional coverage modeling
      * Think of sets
   * 67: Expressions in bit string literal specifications (to allow parameterized sizing based on a static value - ie generic)
      * AI: Brent ask Tristan and/or Lieven why this is so hard.
   * 68: Required Resolution
      * Need to look into if this is even necessary as David Koontz pointed out simulators should produce an error which would satisify this proposals goals.
      * Is this an LRM or tool issue given the LRM already indicates it is an error?
      * Need to run simulation of: process begin CLk &lt;= '1' ; wait for 1 ps ; Clk &lt;= '0' ; wait for 1 ps ; end process ; with simulator resoluton of 1 ns
   * 69: Relax Others in aggregates
      * Forward this to Tristan and/or Lieven
   * 70: Record Member Attribute
      * Introspection of the record via iteration
      * Associated with mapping within interface/bundle procedures
      * may be able to use 'simple_name
      * May be a required part of anonymous types
   * 71: Bidirectional Connections
      * Linked to interface/bundle proposal
      * AI: Lieven consider this with the interface/bundle proposal
   * 72: Optional Semicolon on entity interfaces
      * AI: Rob integrate the other proposal into this.
   * 73: Function Knows Vector Size
      * Too much complexity without simplifying the code - adds discontinuities to the language.
   * 74: Cross language Instances
      * Can this be part of the DPI proposal?
      * AI: Peter Flake
---++ Review and Approve Meeting Minutes:

NA

---++ Next Meeting: Thursday [[2016_MeetingMay19][May 19, 2016]], 11 am Pacific 
---+++ Previous Meeting: Thursday [[2016_MeetingApril28][April 28, 2016]]
Topic revision: r3 - 2020-02-17 - 15:36:17 - JimLewis
P1076