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<!-- Set ALLOWTOPICCHANGE = P1076AdminGroup --> ---+!! P1076 March 10, 2016 Meeting Minutes ---++!! Attendees: Rob Gaddi, Ernst Christen, Lieven Lemiengre, Patrick Lehmann, Peter Flake ---++!! Agenda: %TOC% ---++ Meeting Discussion * What's Next - see [[PrivateDocuments]] file: _summary_vhdl_requirements_priority.xlsx * Further discussion of reflection into records. * Are variant records required? * Can we work with just typeish information (is_array, is_record sorts of things) or do we need to actually maintain the type at runtime? * 'left and 'right are already carried for runtime introspection on array types, but this is an order of magnitude simpler than the variant data of an array * Can we come up with a simpler solution if the only goal is serialization/deserialization? * Requirements for this really need definition, or we're just going back and forth. * 49: [[WaitRepeat][Wait with repeat count]] * Can already be accomplished with for loops * Would provide a slightly cleaner syntax, but would add a keyword to the language. * No one really pushing hard for it, looks like a no * 50: [[MapSubprogramGenericOnCall][Map Subprogram Generics on call]] * <span data-mce-mark="1" style="background-color: #fbfbfb;">Could lead to an explosion in function overloading resolution complexity</span> * <span data-mce-mark="1" style="background-color: #fbfbfb;">Ernst and Lieven feel pretty strongly that this gets messy</span> * Low ROI * <p>51: [[AssertApi][API for VHDL Assert Statements]]</p> * Tabled until Jim Lewis gets back. * 52: [[IntegerOperators][Additional Operators to Integers]] * Would force a definition onto how integers are implemented under the hood, which is currently undefined. * Though the implemention is is _probably_ already all 2's compliment. * Could this be implemented as a trial package? Would probably have to pad asserts around to check for things. * Seems to somewhat merge integer and numeric_bit, which already does all these logic operator things. * MyHDL support modular integers successfully * Lieven will take a run at it * 53: [[SliceMultidimensionArrays][Slicing Multidimensional Arrays]] * Has problems with the memory layout of the data; slices have non-consecutive data. * http://www.eda.org/vhdl-200x/vhdl-200x-ft/proposals/ft15_multidim_slices.txt * PoC has a vectors package that handles such things. https://github.com/VLSI-EDA/PoC/blob/master/src/common/vectors.vhdl * Doing this without copying would require the slice views to have to carry a lot of "stepping" information. Copying is simpler, but slow, and breaks the link to the source data. * Could slow down ALL array accesses. What would the performance implications be? * Can the problem be worked around with arrays of arrays? * This has had very little activity since 2004. * Arrays/composites of protected types. * Need some input from compiler writers as to why we currently disallow this. * Left off at 54. ---++ Review and Approve Meeting Minutes: Lieven approves, Ernst seconds. ---++ Next Meeting: Thursday March 24, 2016 11 am Pacific ---+++ Previous Meeting: Thursday [[2016_MeetingMarch3][March 3 2016]]
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Topic revision: r4 - 2020-02-17 - 15:36:17 -
JimLewis
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