(r3) 2016_MeetingJune9 < P1076

P1076 Web>Vhdl2019MeetingMinutes>2016_MeetingJune9 (revision 3) (raw view)~~EditAttach~~
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---+!! P1076 June 9, 2016 Meeting Minutes
---++!! Attendees:

   * Patrick Lehmann, Lieven Lemiengre, Rob Gaddi, Jim Lewis, Kevin Jennings

---++!! Agenda:

%TOC%

---++ Meeting Discussion
   * Review [[PrivateDocuments]] file: _summary_vhdl_requirements_priority.xlsx
   * Restart at line 94 Next week restart at 104
   * [[SequentialSignal][Sequential Signal Declarations]]
      * Needs use cases
      * some day but not now
   * [[ConditionalReturn][Conditional Return statements]]
      * Amounts to syntax regularization
      * Do return when else ... if easy enough. Otherwise, just when.
   * [[RecommendErrorMessages][Recommended Error Messages]]
      * Opinion of the meeting attendees is that this is a not a good idea
   * [[MixedSignalSupport][Mixed Signal Support]]
      * Seems like something for VHDL-AMS. Does not seem like a topic for VHDL.
      * Get input from Ernst
   * [[MultiCyclePath][Multi Cycle Path]]
      * Either overlap with Clocked Short hand or belongs in a synthesis standard
   * [[TruthTable][Truth Tables]]
      * From ISAC: http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2060.txt
      * no supporters.
      * Can be implemented with a array of an array and a look up into it
   * [[RangeOperations][Range Operations]]
      * http://www.eda-twiki.org/isac/IRs-VHDL-2002/IR2072.txt
      * Definite interest, but do we have time? Is it important enough?
      * Important to keep in mind with other proposals that are in progress
   * [[AsynchronousChannels][Asynchronous Channels]]
      * Can do some of this with protected types.
      * Protected types are missing event semantic when one word is read and another word is available.
      * Missing use model. Proposal needs work in order to be actionable.
   * [[AtomicComposites][Atomic Composites]]
      * Origin targeted at improving simulator performance
      * Need someone interested in working on this
   * [[OverloadAssignment][Overload Assignment vs impicit conversion of expressions at certain points<br />]]
      * Alternately implicitly convert expressions just before an assignment
      * May need to reconsider when we implement arbitrary sized integers
   * [[FunctionKnowsVectorSize][Function Knows Vector Size]]
      * If don't know size?
      * Assume maximum length of argument or error.

---++ Review and Approve Meeting Minutes:

Rob, Lieven

---++ Next Meeting: Thursday [[2016_MeetingJune16][June 16, 2016]], 11 am Pacific
---+++ Previous Meeting: Thursday [[2016_MeetingJune2][June 2, 2016]]
Topic revision: r1 - 2020-02-17 - 15:36:17 - TWikiGuest
P1076