TWiki
>
P1076 Web
>
Vhdl2019MeetingMinutes
>
2016_MeetingApril7
(2020-02-17,
JimLewis
)
(raw view)
E
dit
A
ttach
<!-- Set ALLOWTOPICCHANGE = P1076AdminGroup --> ---+!! P1076 April 07, 2016 Meeting Minutes ---++!! Attendees: * Rob Gaddi, Lieven Lemiengre, Jim Lewis, Brent Hayhoe, Ernst Christen, Patrick Lehmann ---++!! Agenda: %TOC% ---++ Meeting Discussion * What's Next - see [[PrivateDocuments]] file: _summary_vhdl_requirements_priority.xlsx * Restart at line 60 * 60: Array Type Generics * Currently cannot do array type operations on a generic type * No way to enforce that the actual is an array type * <span style="background-color: transparent;">May overlap with abstract packages</span> * May overlap with anonymous types discussion * Should we be able to restricted a type to a scalar type or an array type. * Current sense of the language is that the object is limited to operations on a scalar type * 63: Abstract Packages * Skipped to here due to overlap with 60 * Currently can pass functions * Ernst: Alternative make checking generic package is to parse a generic package as a template and defer the checking until compiling a generic package instance * Lieven would prefer to use an abstract package * 61: New Predefined Attributes: 'actual and 'formal * For integers want to know the range of the actual that is passed to a subprogram vs having to pass 'low and 'high as parameters * Would not always want to do this as it would slow down all subprograms as the 'low and 'high would need to be implicitly passed by the simulator. * May need to be reconsidered with the integer extensions * Alternative: make range a first class object and have the range explicitly passed in the subprogram * Also see: [[RangeOperations]] * Could create an explicit range record. Make 'range available to return the record type. * solvable? * Nice and useful to have but not exactly must have for the level of complexity and/or time required for this proposal * Push to next revision * 62: Conditional Compilation * If limited to only predefined names is it enough? * Tool type (sim, synth), vendor name, tool name, tool revision, language revision * Could use tool directives similar to encryption * Lexing time vs. Parsing time? * Still contentious, need to talk about this again. * Next Meeting discuss interfaces/bundles ---++ Review and Approve Meeting Minutes: Rob, Brent ---++ Next Meeting: Thursday [[2016_MeetingApril14][April 14, 2016]], 11 am Pacific ---+++ Previous Meeting: Thursday [[2016_MeetingMarch31][March 31, 2016]]
E
dit
|
A
ttach
|
P
rint version
|
H
istory
: r3
<
r2
<
r1
|
B
acklinks
|
V
iew topic
|
Ra
w
edit
|
M
ore topic actions
Topic revision: r3 - 2020-02-17 - 15:36:16 -
JimLewis
P1076
Log In
or
Register
P1076 Web
Create New Topic
Index
Search
Changes
Notifications
RSS Feed
Statistics
Preferences
Webs
Main
P1076
Ballots
LCS2016_080
P10761
P1647
P16661
P1685
P1734
P1735
P1778
P1800
P1801
Sandbox
TWiki
VIP
VerilogAMS
Copyright © 2008-2026 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki?
Send feedback