(r3) 2015_MeetingDecember3 < P1076

P1076 Web>Vhdl2019MeetingMinutes>2015_MeetingDecember3 (revision 3) (raw view)~~EditAttach~~
<!--
Set ALLOWTOPICCHANGE = P1076AdminGroup
-->
---+!! P1076 December 3, 2015 Meeting Minutes
---++!! Attendees:

   * Brent Hayhoe, Rob Gaddi, Lieven Lemiengre, Jim Lewis

---++!! Agenda:

%TOC%

---++ Meeting Discussion
   * The WG needs a vice chair or secretary to help with meeting notices and meeting minutes
   * Continue with Interface Discussion
   * Questions 
      * How do we connect an existing interface, such as SPI to a master that has QSPI?
      * Current model shows SPI derived from QSPI, however, that will not facilitate reuse of existing models.
      * Ryan has a related issue looking for a mapping (his is implicit) between existing records: [[RelatedRecords]]
      * Lieven's proposal suggests usage of functions
      * Separating association/mapping from direction abstractions may be a good idea.
      * How do we connect to a model that does not use a bundle/interface?
   * Meeting are posted at: http://www.synthworks.com/2015-12-03%2011.01%20IEEE%20VHDL%20Working%20Group.mp4

We toyed with some syntax for map functions. Keep in mind all syntax is RAW and is the result of brain storming. The following is one idea:
<verbatim>
map function select_qspi_slave(
        master: spi_record;
        slave: spi_slave;
        constant i : ssel_rng) generate
 
begin
        master port map (
                mosi(0) => slave.din,
                miso(0) => slave.dout,
                ssel(i) => slave.cs,
                sclk => sclk
        );
end map function select_qspi_slave;
</verbatim>

Another idea is:
<verbatim>map function qspi_master_to_slave master: spi_record to slave : spi_slave (constant i : ssel_rng) is
begin
  map (
    mosi(0) => din, 
    miso(0) => dout, 
 ... 
</verbatim>

One idea that is currently orphined is mapping in a control interface, such as clk and reset, to multiple different interfaces. Without showing the components, we need to connect ctrl_if that is driven by the ClkReset entity to the s_if and p_if interfaces. Both s_if and p_if include ctrl_if by composition.
<verbatim>
architecture tb of testbench is
    signal ctrl_if : ctrl_interface ;
     interface s_if : s_inteface ;
  begin     
    -- open association mapping candidate 1:
    s_if.ctrl_if <=> ctrl_if ; 
    p_if.ctrl_if <=> ctrl_if ; 

    -- open association mapping candidate 2
    map (s_if.ctrl_if => ctrl_if) ; 
    map (p_if.ctrl_if => ctrl_if) ; 
    
    -- open association mapping variation of candidate 2
    map (
      s_if.ctrl_if => ctrl_if, 
      p_if.ctrl_if => ctrl_if
    ) ; 

     -- A longer more verbose option
    s_if <=> ctrl_if map (s_if.ctrl_if => ctrlif) ; 
</verbatim>

---++ Review and Approve Meeting Minutes:
   * NA
---++ Next Meeting: Thursday December 17, 11 am Pacific
---+++ Previous Meeting: Thursday [[2015_MeetingNovember19][November 19, 2015]]
Topic revision: r1 - 2020-02-17 - 15:36:15 - TWikiGuest
P1076