2014_MeetingMay1 < P1076

P1076 Web>Vhdl2019MeetingMinutes>2014_MeetingMay1 (2020-02-17, JimLewis) (raw view)EditAttach
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---+!! P1076 May 1, 2014 Meeting Minutes
---++!! Attendees:
   * Main.PeterFlake * Main.JimLewis * Main.CliffordWalinsky * Main.StevenDovich
---++!! Agenda:

%TOC%

---++ Group Action Item List
   * All: Review [[http://www.eda.org/twiki/bin/view.cgi/P1076/Vhdl2019ActiveIRTwiki][ISAC Accepted Items Review]]
   * All: Rank Proposals
   * All: Review Proposals
---++ Action Item Review

*Marked completed before meeting*
   * [[BidirectionalConnections][Done]] Jim - 2007 add link in bidirectional connections proposal to 2007
   * [[ConditionalCompilation][Done]] Jim - 2009 - add link from conditional compilation proposal to this and vice versa.
   * [[DynamicRewiring][Done]]- 2021 - Dynamic hardware construct
   * [[ComponentDerivedFromEntity][Done]] - 2011 - Syntax that creates a component declaration from an entity decalaration and puts it into a specified package

*Check status during meeting*
   * Open - revive 1076.6 to handle syntheis proposals on collected requirements page [[MeetingAugust25]] [[MeetingAugust11]] 
      * [[SynthesisAttributes][Synthesis Attributes]] - Package of attributes in 1076?
   * Ryan: Arbitrary width float: see [[2012_MeetingNovember8][Nov 8 2012 meeting]]
   * Open - Multi dimensional Array restructuring: Array &lt;--&gt; Matrix Transformations [[2012_MeetingJuly19]] [[MeetingDecember15]]
   * Ryan - Slicing Multidimensional Arrays (FT15) maybe related to above [[2012_MeetingMay24]]
   * David Bishop: Bugzilla 17 - add_carry in numeric_std as well as fixed/floating packages 
      * Is it already in the fixed and floating point packages?
   * David Bishop: Bugzilla 15 - Should numeric_bit/std have resize with size_res parameter? 
      * David proposed it for consistency with the fixed and floating point packages
   * David Bishop - 262 - Fixed Generic Pkg and checking valid range
   * Jim - Fork and Join [[2012_MeetingJune21]] 
      * Original Verilog, simple fork and join - not used much. Hence, not much value in implementing a simple mechanism
      * SV - more complicated and have ability to kill later
      * Add template proposal and move to "not now" list
   * Jim - Mark bugzillas for which we have a proposal with that status
   * Jim - Table driven modeling via protected types [[2012_MeetingMay10]]
   * David Koontz - Simulation Controls [[MeetingAugust11]]
   * Open - IR 2108 - Level sensitive check - A "wait" that checks condition before stopping 
      * Cliff - Look into passing an expression to a input signal parameter (2008 allows this for an input signal port)
   * Jim - 2109 - Requests semaphore implementation via a protected type 
      * Requires wait inside of a protected type
      * ?Requires signal inside of a protected type?
      * Also interested in a resolution function based semaphore implementation
   * Jim - 2113 - Init ROM / Array data structure using file read 
      * Add textio read to 1076.6 list
      * Add open source family of read array functions to initialize RAM/ROM
   * [[DeferredSharedVariables]] Cliff - 2119 - declare a protected type and object of that type in a single package
   * Jim - 2125 - Resolving 'Z' and '-' results in 'X" rather than '-'
   * Jim - 2003 - simulating and synthesizing multi-cycle paths 
      * Waveform assignment (multiple after) would be appropriate here, if a synthesis tool can handle it.
   * Peter - 2012 - Wants to remove the priority from if-elsif-elsif structures under some conditions. Proposes: "if elsor elsor". 
      * [[http://www.eda.org/twiki/bin/view.cgi/P1076/UniqueCondition][UniqueCondition]]
      * Jim - find examples from OP
---++ [[Vhdl2019ActiveIRTwiki][ISAC Accepted Items Review]]
   * Make sure all items have a tracking proposal
   * OPEN - 2026 - Upward propagating Generics. 
      * Would an external name reference to a constant accomplish some of the intent here?
      * An "OUT" generic would need to have similar constraints to the external name usage.
      * One use models: Out generic of one design connecting to in generic of another.
      * Need other use models
   * OPEN - 2033 - Increment operator with modulo wrap around. 
      * One Option: Does ADA do something like this? Can it be done as a subtype constraint?
      * Another Option: Add inc / dec packages or to standard packages?
   * 2034 - Link into clocked short hand [[ClockedShorthand]]
   * 2035 - Link into clocked short hand [[ClockedShorthand]]
   * 2041 - Link into [[Partiallyconnectedvectorsonportmap]]
   * Bugzilla 293 - link into [[AlternatePathName]]
   * Bugzilla 283 - Resolved as Invalid
---++ Review and Approve Meeting Minutes:
   * Motion: Peter 2nd: Cliff
---++ Next Meeting: [[2014_MeetingMay15][Thursday May 15, 2014]] 8 am Pacific
---+++ Previous Meeting: [[2014_MeetingApr3][Thursday April 3, 2014]]
Topic revision: r4 - 2020-02-17 - 15:50:29 - JimLewis
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