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<!-- Set ALLOWTOPICCHANGE = P1076AdminGroup --> ---+!! P1076 June 26, 2014 Meeting Minutes ---++!! Attendees: * Main.CliffordWalinsky * Main.JimLewis * Main.DavidBishop * Main.StevenDovich * ---++!! Agenda: %TOC% ---++ Action Item Review *Items marked completed before meeting* * [[http://www.eda.org/isac/IRs-VHDL-2002/IR2125.txt][ISAC IR2125]] [[StdulogicResolution]] Done * Proposes either modifying Resolved or creating an alternate one * Recommends creating an alternate one in an open source package * [[http://www.eda.org/isac/IRs-VHDL-2002/IR2113.txt][ISAC IR2113]] [[ReadRom]] Done * Proposes creating types and File IO functions for Memory Arrays * David has seen a ReadMemV. It would be convenient to use that naming. * [[http://www.eda.org/isac/IRs-VHDL-2002/IR2003.txt][ISAC IR2003]] [[MultiCyclePath]] Done * Creates a tracking proposal without any solution. * [[http://www.eda.org/isac/IRs-VHDL-2002/IR2108.txt][ISAC IR2108]] [[WaitLevel]] Done * Level sensitive check - A "wait" that checks condition before stopping * Focus is on updating language to support passing an expression to a input signal parameter, however, as pointed out in the proposal this has issues since an expression passed to a signal parameter will have the left most value of the type. Here that is ok since it is false. * [[ObjectOrientation][Object Orientation]] - Done * Jim: added tracking proposal done * Needs justification and use models added to proposal * Added links to Peter's protected type proposal, Suave, and VHDL Plus * [[DynamicProcessInstance][Dynamic Processes, Instances, Fork and Join]] - Jim: Added Tracking Proposal * [[2012_MeetingJune21]] * Original Verilog, simple fork and join - not used much. Hence, not much value in implementing a simple mechanism * SV - more complicated and have ability to kill later * [[MultipleDesignHierarchies]] * Cliff: Multiple Hierarchy Roots * Monitor Entity/Architecture watching things in the design, ... *Things Done During Meeting* * Need more reviewers of matrix math package * Ryan, Martin * Building a list of change proposals * Proposal of operators such as ".*" * P1735 - Is in its finalization stages. * Steve to start on reconciliation into what we need to update in VHDL * Open - technical leader for 1076.6 activities? * std_logic_1164 uses 1076.6 attribute "RTL_SYNTHESIS_OFF" and "RTL_SYNTHESIS_ON" * Martin - 2033 - Increment operator with modulo wrap around. * One Option: Does ADA do something like this? Can it be done as a subtype constraint? * Another Option: Add inc / dec packages or to standard packages? * Ryan: Arbitrary width real: see [[2012_MeetingNovember8][Nov 8 2012 meeting]] * Open - Multi dimensional Array restructuring: Array <--> Matrix Transformations [[2012_MeetingJuly19]] [[MeetingDecember15]] * Matlab has built-in reshape functions * In VHDL - explicit vs implicit defined operator * David Bishop: Requiring an implicit operator could delay implementations * Can this be handled by anonymous types on interfaces or generics on a package? * Language facility for creating implicit operators? * Ryan - Slicing Multidimensional Arrays (FT15) maybe related to above [[2012_MeetingMay24]] * David Bishop: Bugzilla 17 - add_carry in numeric_std as well as fixed/floating packages * In the fixed point package, but not floating point package. * Not in numeric_std. Add for consistency? * David Bishop: Bugzilla 15 - Should numeric_bit/std have resize with size_res parameter? * David proposed it for consistency with the fixed and floating point packages * David Bishop - 262 - Fixed Generic Pkg and checking valid range * Jim - Mark bugzillas for which we have a proposal with that status * Jim - Table driven modeling via protected types [[2012_MeetingMay10]] * Jim - 2109 - Requests semaphore implementation via a protected type * Requires wait inside of a protected type * ?Requires signal inside of a protected type? * Also interested in a resolution function based semaphore implementation * OPEN - 2026 - Upward propagating Generics. * Would an external name reference to a constant accomplish some of the intent here? * An "OUT" generic would need to have similar constraints to the external name usage. * One use models: Out generic of one design connecting to in generic of another. * Need other use models ---++ Ranking Criteria * Rank based on need * Item needs to be fixed * Useful for an application * Rank based on complexity * How hard to implement * Noted several items in Collected Requirements as Must Do * AI: Jim: Create ranking sheet. ---++ Review and Approve Meeting Minutes: * Motion: Cliff 2nd: Steve ---++ Next Meeting: Thursday [[2014_MeetingJuly10][July 10, 2014]] 8 am Pacific ---+++ Previous Meeting: Thursday [[2014_MeetingJune12][Thursday June 12, 2014]]
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