2013_MeetingJune27 < P1076

P1076 Web>Vhdl2019MeetingMinutes>2013_MeetingJune27 (2020-02-17, JimLewis) (raw view)EditAttach
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---+ P1076 June 27, 2013 Meeting Minutes
---++ Attendees:
   * Main.JimLewis * Main.PeterFlake * Main.CliffordWalinsky * Main.RyanHinton * Main.JarekKaczynski

---++ Agenda:
   * Revisit VHDL-2008-MP items (just 2 to revisit, notes from last meeting copied here)
   * Review VHDL-2008-TBV 6, 9, and 13
   * Check closure on AI from review lists.
   * See these items in the <a target="_top" href="Vhdl2019CollectedRequirements">collected requirements list</a>
---++ Review of VHDL-2008-MP
   * MP - Remove white space requirement in physical literals 
      * A small issue, not necessarily worth doing this revision.
      * Ambiguity if have a physical literal identifier named 'e' and bit string literals
      * Confusing for those who work in mixed language environments.
      * SystemVerilog requires no space with their physical literals.
      * Drop for this revision

   * MP - Longest static prefix issue with loops 
      * If Globally static, may be solvable. Cliff to continue looking into it.

---++ Review of VHDL-2008-TBV 6, 9, and 13
   * TBV 6 - Assign image values for identifier-based enumeration type values 
      * VHDL term image does not have any meaning here.
      * Assuming it wants to impact the state mapping of a statemachine
      * type StateType is (S0 := 3, S1 := 5, S3 :=6) ;
      * Does it redefine position values (is it ok having 'pos be sparse?) or
      * is it some new thing with its own version of 'pos and 'val
      * Historically its has been done with attributes. 
         * attribute enum_encoding of TxStateType : type is "0011 0110 1100 0101 1010 1001" ;
      * Could instead create new attribute based on integer_vector that would accomplish the same thing. 
         * Make the attribute a standard attribute.
      * Is it worth doing? 
         * Ryan - probably would not use.
         * Drop

   * TBV 9 - Expected Value Detectors 
      * Create a verification library / package.
      * Need further information on requirement.
      * Drop for lack of information.

   * TBV 13 - Object Orientation 
      * Suave? 
         * Is there a Suave pre-compiler that would translate suave code into regular VHDL?
      * Protected Types? 
         * Have a fairly complete proposal
      * What is the target application?
      * Used by system level designers?
      * ADA style vs C style? 
         * System level designers commonly use C
      * Can we solve this by binding to C and/or ADA? 
         * Does the DPI proposal cover this?
      * Add to proposal list and address during ranking of proposals.

---++ Review and Approve Meeting Minutes:
   * Motion: Jerry 2nd: Ryan
---++ Next Meeting Date:

Thursday July 18, 8 am Pacific
Topic revision: r4 - 2020-02-17 - 15:36:12 - JimLewis
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