2013_MeetingJune13 < P1076

P1076 Web>Vhdl2019MeetingMinutes>2013_MeetingJune13 (2020-02-17, JimLewis) (raw view)EditAttach
<!--
   * Set ALLOWTOPICCHANGE =  P1076AdminGroup
-->
---+ P1076 June 13, 2013 Meeting Minutes
---++ Attendees:
   * Main.JimLewis * Main.PeterFlake * Main.CliffordWalinsky * Main.JarekKaczynski

---++ Agenda:
   * Review VHDL-2008-MP remaining list items
   * Review VHDL-2008-TBV 6, 9, and 13
   * Check closure on AI from review lists.
   * See these items in the <a target="_top" href="Vhdl2019CollectedRequirements">collected requirements list</a>

---++ Review of VHDL-2008-MP
   * MP6: Allow attribute declarations in code regions (not just declaration regions) 
      * Benefit: keeps attributes which control synthesis local with the code they modify
      * No compelling discussion either way.
      * Not for this revision
   * MP8 - Make transport the default delay mode 
      * Breaks backward compatibility
      * not a high list
      * Concern about breaking backward compatibility
      * Not for this revision
   * MP - Allow subprogram bodies in package declarations 
      * Benefit: removes extra declartion of package interface
      * May cause issues with encryption?
      * May complicate analysis process.
      * Jim thinks current requirements make big packages more readable.
      * Not for this revision
   * MP - Ability to apply register kind semantics to std_logic. Retain last resolved value when all drivers are off 
      * Not clear what this is trying to get at.
      * Drop.
   * MP - Remove white space requirement in physical literals 
      * Confusing for those who work in mixed language environments.
      * Do common simulators allow dropping of the space?
      * SystemVerilog requires no space with their physical literals.
      * A small issue, not necessarily worth doing.
      * Revisit in next meeting.
   * MP - Short alias name for std_logic_vector 
      * Short names increase likelyhood of finding other items also.
      * Complicates global search and replace
      * Concerns about conflicting with user names
      * Drop
   * MP - Value folding of std_ulogic (2 state/4 state) 
      * Not clear
      * Discussion is tending toward multiple packages.
      * Need a more firm understanding of what is wanted and rationale.
      * Drop
   * MP - Implicit generic/port map in component instance 
      * have proposal for [[ImplicitConnections][Implicit Parameter and Port Connections]]
      * Already have a proposal.
   * MP - Add Endif (like elsif) 
      * If we add EndIF, then do we need EndProcess, EndArchitecture
      * Drop.
   * MP - One_hot assertion to remove priority from if-then-elsif 
      * Would be a package based
      * Accept. Need proposal
      * Make name consistent with PSL, and SystemVerilog (if possible).
   * MP - Longest static prefix issue with loops 
      * Is this solvable?
      * Good thing about current situation: 
         * Expensive to assign to elements of an array in a loop.
         * Preferred method: use temporary variable array, fill it up, and assign it to a signal.
      * AI: Cliff to look into this.
      * Revisit in next meeting.
---++ Review and Approve Meeting Minutes:
   * Motion: Jerry  2nd: Peter
---++ Next Meeting Date:

Thursday June 27, 8 am Pacific
Topic revision: r3 - 2020-02-17 - 15:36:12 - JimLewis
P1076