2012_MeetingDecember20 < P1076

P1076 Web>Vhdl2019MeetingMinutes>2012_MeetingDecember20 (2020-02-17, JimLewis) (raw view)EditAttach
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---+ P1076 December 20, 2012 Meeting Minutes
---++ Attendees:
   * Main.CliffordWalinsky * Main.PeterFlake * Main.JimLewis * Main.HansTiggeler * Main.JarekKaczynski
---++ Agenda:
   * Login to get the [[DialInInfo][Dial-in Information]]
   * Call for proposals for new items
   * Call for volunteers to work on proposals
   * Looking for team leader for ISAC
   * Review updated proposals 
      * [[http://www.eda.org/twiki/bin/view.cgi/P1076/WebRss][RSS of recent changes]]
   * Review requirements lists from VHDL-200X/Accellera effort 
      * Assign owners to raw items and work toward proposals
   * Review items in the [[http://www.eda.org/twiki/bin/view.cgi/P1076/Vhdl2019CollectedRequirements][collected requirements list]]
   * Review [[IssueScreening][ISAC issues and Bugzilla]]
---++ Deferred Shared Variables
   * Candidate1: Marking Deferred
   * Candidate2: Allow protected type bodies (and potentially subprogram bodies) within package declaration
   * CliffW: Concerned about compiler complexity of either candidate
   * We need code examples to justify consideration of the complexity.
   * Cliff and Jarek will ask about the complexity of this.
---++ Register Definitions
   * SystemRDL - Accellera Standard - human readable
   * IP-XACT - XML based
   * SystemC and SystemVerilog have packages that use this
   * Maybe tools that already handle this.
---++ Closely Related Record Types
   * Seems to be quiet now
   * All in meeting concur closely related records should require that record elements must match by name and position and field types must be closely related.
   * Action Jim: Add examples from email to the proposal to demonstrate current languge support for mapping
---++ Review and Approve Meeting Minutes:
   * Motion: Peter 2nd: Cliff
---++ Next Meeting Date (proposed):

Thursday January 3, 8 am Pacific
Topic revision: r3 - 2020-02-17 - 15:36:11 - JimLewis
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