Subject: [vhdl-200x-perf] Re: Performance issues
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue Apr 29 2003 - 12:43:19 PDT
One reason Verilog is faster than VHDL is that has "blocking" assignments
which propagate signal changes immediately to other modules rather than
"non-blocking" where the change is scheduled for the next delta or later.
VHDL only has the later which always incurs an extra scheduling/descheduling
overhead.
You could speed VHDL up by adding a "blocking" assign.
Note: the trade-off is speed vs. stability, blocking assigns lead to
intrinsically
racy behavior. The better way to get a speed up is to use parallel
processing
in which case you want the more stable behavior.
Kev.
-- National Semiconductor, Tel: (408) 721 3251 2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090
This archive was generated by hypermail 2b28 : Tue Apr 29 2003 - 12:44:24 PDT