Subject: RE: [vhdl-200x-perf] Re: Performance issues
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri May 02 2003 - 10:46:41 PDT
Another difference between Verilog & VHDL is that Verilog allows
processes to share a driver via the "reg" declaration. That
allows you to behaviorally model circuits with a single output
from multiple (asynchronous) internal state machines more
efficiently than VHDL.
You could possibly get some speed up by making drivers an
explicit object in VHDL, rather than just the implicit interface
between a process and a signal. It would make translating
Verilog into VHDL somewhat easier too.
Kev.
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