Subject: Re: [vhdl-200x-perf] Re: Performance issues
From: Stephen Bailey (stephen@srbailey.com)
Date: Tue Apr 29 2003 - 15:41:23 PDT
VHDL does have the equivalent. They are called shared variables. Also, I think you would have a difficult time finding more than 1
or 2 people from the VHDL user community that would want the Verilog race problem introduced into VHDL.
Nonetheless, the Performance group has a request for light-weight signals which covers this area.
-Steve Bailey
> One reason Verilog is faster than VHDL is that has "blocking" assignments
> which propagate signal changes immediately to other modules rather than
> "non-blocking" where the change is scheduled for the next delta or later.
> VHDL only has the later which always incurs an extra scheduling/descheduling
> overhead.
>
> You could speed VHDL up by adding a "blocking" assign.
>
> Note: the trade-off is speed vs. stability, blocking assigns lead to
> intrinsically
> racy behavior. The better way to get a speed up is to use parallel
> processing
> in which case you want the more stable behavior.
>
> Kev.
>
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