Subject: RE: [vhdl-200x-perf] Re: Performance issues
From: Jay Lawrence (lawrence@cadence.com)
Date: Wed Apr 30 2003 - 06:56:14 PDT
Speaking for one vendor, a lot of the discussion around immediate (i.e.
Verilog blocking assignments) vs delta delay vs unit delay to VHDL
signals is really moot. We already identify delta delay assignments and
perform significant optimizations on them. They can be both scheduled
and executed in constant time. I assume the other vendors do these as
well because they are so common and lead to significant gain.
I personally believe immediate assignment would be disasterous for race
conditions and given that delta delay assignments are highly optimizable
they do not have significant impact on performance while preserving
determinism.
Jay
===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Paul J. Menchini [mailto:mench@mench.com]
> Sent: Wednesday, April 30, 2003 9:38 AM
> To: Steve Casselman
> Cc: vhdl-200x-perf@eda.org
> Subject: Re: [vhdl-200x-perf] Re: Performance issues
>
>
> Steve,
>
> > Would you get a race condition if you had unit delay? So
> this is kind
> > of what I was talking about before you'd have to be a real expert to
> > know to use a shared variable and then if you wanted to
> switch between
> > accuracy and speed you would have to change your code (or
> make it much
> > more complicated). It would be great if there was a simple
> switch or
> > change of library that told the simulator to swap in all the tricky
> > fast stuff and then go back to the slower more accurate models when
> > you get near the end of your design cycle. Some way where all the
> > expert trade offs for speed vs accuracy are done in the standard and
> > the end user just has to specify the "fast" or "accurate" system.
>
> No, you would not have a race condition if you introduced unit delay.
> VHDL has these, but their called "delta delays." If you were to make
> shared variables update only with unit delay, you'd then turn
> them into
> VHDL signals.
>
> As to the switch, there's nothing preventing vendors from doing this.
> It would be an interesting question to ask them if they have, and if
> not, why not.
>
> Paul
>
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