Re: [vhdl-200x-ft] Revised FT18: condition operator

Selon Jim Lewis <Jim@SynthWorks.com>:

> >>It is sad as if we had never had boolean, the "=" above
> >>could have propagated 'X's if a bit of Addr had an 'X' or
> >>ignored bits if a bit of REG1_ADDR contained '-'.
> >>As it stands, "=" must coerce things into true/false.
> >
> > Sure, but this is due to the if statement. In a if/else statement you have
> to
> > choose. In a if/else statement, 'X' has no meaning.
> Consider the following when A = 'X':
> not (A = '1') vs (not A) = '1'
>
> It is not a just a function of the if-then it is also a
> function of when the conversion to boolean happens.
> The later it can happen the better.
>
> If boolean did not exist and instead we used a type in which
> everything resolved to X, 0, and 1 (like std_ulogic after
> applying to_x01), then we could potentially have more
> accurate results.
I don't understand how results would be more accurate in an if/else statement.
That's a trap with Verilog: x does not propagate through if statement.
In VHDL you do not have the problem, since a boolean has no x.
Furthermore, in VHDL you can trap x, by defining an (impure) function which
convert std_ulogic to boolean and emit a report if the value is x,z,-,w,u.

Tristan.
Received on Fri Dec 10 03:49:28 2004