Re: [vhdl-200x-ft] Revised FT18: condition operator

From: Jim Lewis <Jim@SynthWorks.com>
Date: Thu Dec 09 2004 - 16:40:05 PST

Tristan,
>>I see it as replacing (data-flow):
>> Reg1Sel <= '1' when DevSel = '1' and Addr(2 downto 0) = REG1_ADDR
>> else '0' ;
>>
>>With (?data-flow?):
>> Reg1Sel <= DevSel and (Addr(2 downto 0) = REG1_ADDR) ;
      std_logic std_logic ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                                     boolean

Currently there is no standard function that allows anding
std_ulogic with boolean and return a std_ulogic.

>>It is sad as if we had never had boolean, the "=" above
>>could have propagated 'X's if a bit of Addr had an 'X' or
>>ignored bits if a bit of REG1_ADDR contained '-'.
>>As it stands, "=" must coerce things into true/false.
>
> Sure, but this is due to the if statement. In a if/else statement you have to
> choose. In a if/else statement, 'X' has no meaning.
Consider the following when A = 'X':
   not (A = '1') vs (not A) = '1'

It is not a just a function of the if-then it is also a
function of when the conversion to boolean happens.
The later it can happen the better.

If boolean did not exist and instead we used a type in which
everything resolved to X, 0, and 1 (like std_ulogic after
applying to_x01), then we could potentially have more
accurate results.

Regards,
Jim

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787
Expert VHDL Training for Hardware Design and Verification
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Received on Thu Dec 9 16:40:08 2004

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