Re: [vhdl-200x-ft] Revised FT18: condition operator

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On Friday 03 December 2004 17:10, Jim Lewis wrote:
> Tristan,

[...]

> > I was not clear enough. In the second form (the one I have written),
> > the "??" function is always implicitly called at the highest level of a
> > condition. Therefore, boolean is not that special anymore (exception
> > that only function "??" returning a boolean are considered).
>
> Agree.
> As long as it is only implicitly called one time we are ok.

So we are both OK on this point.

[...]

> > That's a real debat, and it seems you like Verilog point of vue on this
> > issue!!!
> > I do like strong typing and I do like the difference between boolean and
> > bit/std_logic. It clearly separates data-flow from control-flow.
>
> I like strong typing too. I just hate boolean.
> Imagine VHDL without boolean. I don't see it as
> data-flow vs control-flow.

I can't imagine VHDL without boolean. For two reasons:
* Boolean are meaningful in high-level units (testbenches for example).
* There is no obvious mapping between boolean and bits.

> I see it as replacing (data-flow):
> Reg1Sel <= '1' when DevSel = '1' and Addr(2 downto 0) = REG1_ADDR
> else '0' ;
>
> With (?data-flow?):
> Reg1Sel <= DevSel and (Addr(2 downto 0) = REG1_ADDR) ;

I do not understand this point.
VHDL accept currently both statements.

> It is sad as if we had never had boolean, the "=" above
> could have propagated 'X's if a bit of Addr had an 'X' or
> ignored bits if a bit of REG1_ADDR contained '-'.
> As it stands, "=" must coerce things into true/false.

Sure, but this is due to the if statement. In a if/else statement you have
 to choose. In a if/else statement, 'X' has no meaning.

> To do something more accurate, we would need to introduce
> new operators.

I still don't understand your point.

Tristan.
Received on Sun Dec 19 06:13:58 2004