Re: [vhdl-200x-ft] Implicitly referencing std.textio and library IEEE

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On Friday 03 December 2004 16:14, Jim Lewis wrote:
> Tristan,

[...]

> > I strongly second.
> > I/O are used only in a few units. Therfore, automatically adding them
> > makes analysis bloated.
>
> When compilers took 20 minutes to compile one piece of code,
> this makes some sense, however, now when I can be lazy and
> recompile my entire design (without using make) and rerun
> my simulation in the time it takes me to get coffee, why do
> I worry about bloating analysis.

This is not really a question of time.

> Instead I am worried about adding burden to the user to
> do something basic like printing, and hence, am
> simplifying the world from the user's perspective.

For me, this can be resolve by better ways:
* use a correct editor which automatically add your favorite context_clauses
when you create a new file.
* use the proposed context declarations.
If you want to solve this issues with both context declarations and adding
 new default context clauses, then one of the two alternative is not
 necessary.

> > I strongly recommand not to make IEEE special. That's the beauty and the
> > power of VHDL.
>
> "beauty" (from Tristan) and "simplified" (from John)
> mean nothing unless you explain the technical aspects.

You are right.

> Since I use the IEEE library in basically all of my
> designs, to me it is not a thing of beauty, it is a
> bit of tedious work I must do for every VHDL file.

The technical aspects are:
* Making IEEE special also bloat the LRM. Of course, this is only a few
lines. But the user might not understand why he doesn't declare the IEEE
library and not the Xilinx/Altera/your founder library.
So, this also makes VHDL more orthogonal. This is a strong technical
aspect.
* I don't understand what it tedious work: blame your editor.

> > [Jim:]
> >
> >>>Implicitly referencing std.textio would make usage of
> >>>textio more consistent with the usage model being introducted
> >>>by the other packages (std_logic_1164, numeric_std, ...)
> >>>since they include read and write in them.
> >
> > The mistake is here: why read/write will be included in
> > std_logic_1164/numeric_std ?
>
> Our intent is to simplify VHDL usage from a designer's
> perspective. Does separating these functions from these
> packages help a user? As we add additional types (fixed point
> and floating point) if we put read/write in the base package,
> then the user must reference N packages. If we put read/write
> in separate packages, then the user needs 2*N packages simply
> to be able to print. Is making their (and my) work twice as
> tedious necessary?

Well, this is a methodology. Why having N packages instead of N/2 packages ?
For example, why the content of textio is not in standard ?
Why the content of numeric_std in not in std_logic_1164 ?
There are arguments for both sides of view.
Currently, the VHDL choice was to separate the IO parts. Unfortunately, the
rational is lost (that's another problem with VHDL LRMs: no rational is
available). For me you can explain this choice with the fact that I/O are
not synthesizable. These features are not often used (many designers don't
know how to use them). In VHDL packages, synthesizable features are clearly
separated from non-synthesizable features. Therefore, when you read 'use
textio.all' in a file, you are pretty sure it is a testbench.

You could also explain why putting R/W in separate packages makes you word
tedious ? Is it only because you have to write a few more lines ?

Tristan.
Received on Sun Dec 19 06:12:40 2004