Re: [vhdl-200x] interface proposals

From: Brent Hayhoe <bahayhoe@gmail.com>
Date: Thu Dec 03 2015 - 10:57:28 PST
Hi Tristan,

On 01/12/2015 08:46, tgingold@free.fr wrote:
> ----- Mail original -----
> [...]
>> I think the syntax can accommodate both semantics:
>>
>>
>>      type BitRecType is
>>         generic(
>>            Size : Natural
>>         );
>>         record
>>            A : String (1 to Size);
>>            B : Std_Logic_Vector;
>>         end record BitRecType;
>>
>>      entity BitEntity is
>>         generic(
>>            Size  : Natural := 10;
>>            Width : Natural := 8
>>         );
>>         port(
>>            IP : in  BitRecType( B(Width - 1 downto 0) ) generic
>>            map(Size);
>>            OP : out BitRecType( B(Width - 1 downto 0) ) generic
>>            map(Size)
>>         );
>>      end entity BitEntity;
>>
>>
>> I think that the 'record_constraint' is syntactically differentiated
>
> The fact that there is two possible ways ('generic' and unconstrained
> elements) for the same higher level feature (specifying the size of
> elements) is not a good sign.

Yes, I agree

>
> You haven't answered my first question: is an 'instance' of a type
> with a generic part a new type or the same type ?

Oops forgot about that.

If we limit the generic to a constant generic, then I see it as defining a 
constraint operation and therefore producing a subtype as at present.

I can see a suggestion for allowing type generics within a record composite (and 
maybe arrays) to constrain the the type of an element. In this case, maybe it 
would sensible if the outcome were a new type?

What do you think?

>
> Tristan.
>
>


-- 

Regards,

         Brent Hayhoe.

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Received on Thu Dec 3 10:57:32 2015

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