Re: [vhdl-200x] interface proposals

Hi Brent and All,
I was thinking of a different example from constraining an array.
To me the discriminated record syntax is just a simpler way of
applying a value to something than a generic and it seems to be
able to be applied at usage time.

In addition, I was thinking of applying discriminated record syntax to
a record view.  Drawing from Rob Gaddi's SPI example, this simplifies
it to:

record view qspi_slave (IDX : ssel_rng) of spi_r is
     mosi : in;
     miso : out;
     sclk : in;
     cs   : in std_logic is ssel(IDX)
end record view qspi_slave;

record view spi_slave  (IDX : ssel_rng) of spi_r is
     din  : in  std_logic is mosi(0);
     dout : out std_logic is miso(0);
     sclk : in;
     cs   : in  std_logic is ssel(IDX)
end record view spi_slave;


Then on the entity interface it becomes:

entity qspi_flash
         generic (
                 pkg : spi_bus_pkg;
                 CS  : pkg.ssel_rng;
                 Tpd : time := 1 ns;
                 Ts  : time := 1 ns;
         );
         port (
                 spi  : view pkg.qspi_slave (IDX => CS);
                 wren : in std_logic := 1
         );
end entity qspi_flash;


However, the SPI example seems to expose some flaws.  In Rob's SPI
example, the base type assumes a QSPI.  How do I connect that QSPI
bus with an already designed SPI model?  I should not have to redefine
the type of the SPI model in terms of QSPI.

Hence, it seems like we need a separate association between the types
that perhaps works in a fashion similar to the conversion function that
Lieven has in his proposal.

Also how do I connect to a model that does not use a bundle/interface?

I think I will start a separate thread for these.

Cheers,
Jim



On 11/22/2015 2:56 AM, Brent Hayhoe wrote:
> Some thoughts:
>
> -- So this is the Ada 'discriminated record' type that I presume we are
> -- discussing. The way it looks to me is just a 'constant generic' applied to -- the record type:
>
> type Discriminated_Record (Size : Natural) is
>    record
>       A : String (1 .. Size);
>    end record;
>
> -- So if I VHDL'asize this we could have a generic block preceding the record
> -- block in the type declaration.
>
> -- We then need to 'generic map' the 'Size' value through when we declare a
> -- constant and signals:
>
> type MyRecType is
>    generic(
>       Size : Natural
>    );
>    record
>       A : String (1 to Size);
>    end record MyRecType;
>
> constant MyRecConst  : MyRecType generic map(10) := (A => "0123456789AB");
>
> signal   MyRecSig1   : MyRecType generic map(10) := MyRecConst;
>
> signal   MyRecSig2   : MyRecType generic map(Size => 10);
>
>
> -- Bearing in mind the ability to have a arrays of records, we need to be able
> -- to apply generics to arrays in a similar manner.
>
> -- Now in the type declaration we need to pass the generic through to the
> -- record elements using a generic map construct:
>
> type MyArryType is
>    generic(
>       Size : Natural
>    );
>    array(1 to 20) of
>       MyRecType generic map(Size);
>
> constant MyArryConst : MyArryType generic map(10) :=
>                                        (1 to 20 => (A => "0123456789AB"));
>
> signal   MyArrySig1  : MyArryType generic map(10) := MyRecConst;
>
> signal   MyArrySig2  : MyArryType generic map(Size => 10);
>
>
> -- The syntax suggested above is meant to be similar to that of entities with
> -- generics and the mapping of the generics done at an equivalent instantiation
> -- point.
>
> -- The alternative is to instantiate similar to packages or maybe we allow both
> -- optional forms?
>
> -- Let's assume 'MyRecType' is declared in a package somewhere. We instantiate
> -- it as shown:
>
> type MyRecType_10 is new MyRecType
>    generic map(Size => 10);
>
> constant MyRecConst  : MyRecType_10 := (A => "0123456789AB");
>
> signal   MyRecSig1   : MyRecType_10 := MyRecConst;
>
> signal   MyRecSig2   : MyRecType_10;
>
> -- For the array we may want to now define it as:
>
> type MyArryType_10 is
>    array(1 to 20) of
>       MyRecType_10;
>
> -- This is fine unless we want to keep the generic nature of the array type and
> -- declare it within the package. In this case we need to to use the first
> -- embedded 'generic map' syntax within the array declaration syntax.
>
> -- Maybe we should allow both?
>
> Regards,
>
> Brent.
>
>
> On 19/11/2015 22:05, Jason Borland wrote:
>> That would work very well.
>>
>> Jason
>>
>> Sent from my iPhone
>>
>>> On 19 Nov 2015, at 9:12 p.m., Jim Lewis <Jim@synthworks.com> wrote:
>>>
>>> Hi,
>>> In this weeks meeting some expressed concerns about generics on interfaces.
>>>
>>> ADA has a concept of discriminants that actually may address the situation we
>>> are working with well.  See the web page:
>>> https://en.wikibooks.org/wiki/Ada_Programming/Types/record
>>>
>>> Cheers,
>>> Jim
>>>
>>> -- 
>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>> Jim Lewis
>>> VHDL Training Expert, SynthWorks
>>> IEEE 1076 VHDL Working Group Chair
>>> Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder
>>>
>>> 1-503-590-4787
>>> Jim@SynthWorks.com
>>> http://www.SynthWorks.com
>>>
>>> VHDL Training on leading-edge, best coding practices for hardware design and verification.
>>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
>

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis                                  Jim@SynthWorks.com
VHDL Training Expert                       http://www.SynthWorks.com
IEEE VHDL Working Group Chair
OSVVM, Chief Architect and Cofounder
1-503-590-4787
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~