Re: [vhdl-200x] interface proposals

For Brent's original example, we can rewrite my previous example in an even
more simplified form, i.e. we use the "tlm" package simply as an
uninstantiated package (and not a generic package):

library work.*transactor*.all;
entity MyEntity is
    generic(
       Size : Natural := 10
    );
    port(
       IP : in  *t_data*;
       OP : out *t_data*
    );
end entity MyEntity;

package *tlm* is
    generic(
*        type t_data*
    );
end package tlm;

package *transactor* is new work.*tlm*
    generic map(
*        t_data => u_signed(9 downto 0)*
    );

The user may again change t_data to any other type or width as he/she sees
fit.

Cheers, Dan

On Tue, 24 Nov 2015 at 09:45 Daniel Kho <daniel.kho@gmail.com> wrote:

> Yes, just to add on to what Tristan said, I use generic types as the types
> for I/Os as well. That eliminates the need to put generic maps on
> individual ports (looks kind of weird to me). Anyway, I have something like
> this in many of my existing designs (simplified to just illustrate the
> basic concept):
>
> -- We can have ports that are record types with generic widths.
> -- The "spi" port has a "data" element whose width is parameterizable.
> library work.*spiTransactor*.all;
> entity spiMaster is port(
> *    spi: inout t_spi*
> );
> end entity spiMaster;
>
> -- First, we have a generic package. This will later be used by
> -- another uninstantiated package.
> package *tlm* is
>     generic(
> *        type t_data*
>     );
> end package tlm;
>
> -- We can have an uninstantiated package defined as the following.
> -- This uses a generic package called "tlm", where the elemental data
> structures (such as "t_data") are defined.
> -- These basic structures are generic types whose widths are
> parameterizable.
> package *spiTLM* is
>     generic(
>         package i_spiTransactor is new work.*tlm* generic map(<>)
>     );
>
>     type *t_spi* is record
>         sclk: std_ulogic;
>         mosi: std_ulogic;
>         miso: std_ulogic;
>         nSS: std_ulogic;
>         *din: t_data;*
>     end record *t_spi*;
> end package *spiTLM*;
>
> -- Here we "instantiate" and map the generic package with specific
> user-defined types.
> -- Here is where we can specify what data type and width is to be used for
> the port of the
> -- entity that uses this package (in our case, the "spiMaster" entity's
> "spi" port).
> package *spi0_transactor* is new work.*tlm*
>     generic map(
> *        t_data => u_signed(31 downto 0)*
>     );
>
> package *spiTransactor* is new work.*spiTLM*
>     generic map(
>         i_spiTransactor => work.*spi0_transactor*
>     );
>
> With all the packages already defined, for a user to change the "spi"
> port's data type and width will be easy: Just map the "spi0_transactor"'s
> t_data to a different type or width as the user sees fit.
>
> Best regards,
> Daniel
>
> On Tue, 24 Nov 2015 at 04:40 Tristan Gingold <tgingold@free.fr> wrote:
>
>> On 23/11/15 20:26, Brent Hayhoe wrote:
>> > Hi Tristan,
>> >
>> > On 22/11/2015 11:40, Tristan Gingold wrote:
>> >> On 22/11/15 11:56, Brent Hayhoe wrote:
>> >>> Some thoughts:
>> >>>
>> >>> -- So this is the Ada 'discriminated record' type that I presume we
>> are
>> >>> -- discussing. The way it looks to me is just a 'constant generic'
>> >>> applied to -- the record type:
>> >>>
>> >>> type Discriminated_Record (Size : Natural) is
>> >>>     record
>> >>>        A : String (1 .. Size);
>> >>>     end record;
>> >>>
>> >>> -- So if I VHDL'asize this we could have a generic block preceding the
>> >>> record
>> >>> -- block in the type declaration.
>> >>>
>> >>> -- We then need to 'generic map' the 'Size' value through when we
>> >>> declare a
>> >>> -- constant and signals:
>> >>>
>> >>> type MyRecType is
>> >>>     generic(
>> >>>        Size : Natural
>> >>>     );
>> >>>     record
>> >>>        A : String (1 to Size);
>> >>>     end record MyRecType;
>> >>
>> >> Isn't this a little bit overkill given that it is already possible
>> >> to have unbounded arrays as record elements ?
>> >
>> > Not if you want to do something like:
>> >
>> > entity MyEntity is
>> >     generic(
>> >        Size : Natural := 10
>> >     );
>> >     port(
>> >        IP : in  MyRecType generic map(Size);
>> >        OP : out MyRecType generic map(Size)
>> >     );
>> > end entity MyEntity;
>> >
>> > You could decompose the records at the port, but with bigger record
>> > structures this will become very cumbersome.
>>
>> My point is that this overlaps record_constraint.  What would be the
>> syntax if you have both ?  Would that be readable ?
>>
>> Beside the syntax, the semantic is not clear to me.  When you
>> 'instantiate' a type, is it a new type or a subtype ?
>>
>> The complexity becomes very high.
>>
>> What is wrong with:
>>
>> type MyRecType is record
>>    A : String;
>> end record;
>>
>> entity MyEntity is
>>    port (IP : in MyRecType;
>>          OP : out MyRecType);
>> end MyEntity;
>>
>> [ In Ada, the discriminants is either a discrete type or an access type.
>>   I suppose vhdl is not interested in access type here.  But setting the
>> discriminant doesn't create a new type.  Furthermore it is possible to
>> change the discriminant(s) under some restrictions. ]
>>
>>
>>
>>
>> --
>
> Best regards,
> Daniel
> - Sent from my Samsung mobile -
>
-- 

Best regards,
Daniel
- Sent from my Samsung mobile -