Re: [vhdl-200x] interface proposals

On 23/11/2015 20:40, Tristan Gingold wrote:
> On 23/11/15 20:26, Brent Hayhoe wrote:
>> Hi Tristan,
>>
>> On 22/11/2015 11:40, Tristan Gingold wrote:
>>> On 22/11/15 11:56, Brent Hayhoe wrote:
>>>> Some thoughts:
>>>>
>>>> -- So this is the Ada 'discriminated record' type that I presume we are
>>>> -- discussing. The way it looks to me is just a 'constant generic'
>>>> applied to -- the record type:
>>>>
>>>> type Discriminated_Record (Size : Natural) is
>>>>     record
>>>>        A : String (1 .. Size);
>>>>     end record;
>>>>
>>>> -- So if I VHDL'asize this we could have a generic block preceding the
>>>> record
>>>> -- block in the type declaration.
>>>>
>>>> -- We then need to 'generic map' the 'Size' value through when we
>>>> declare a
>>>> -- constant and signals:
>>>>
>>>> type MyRecType is
>>>>     generic(
>>>>        Size : Natural
>>>>     );
>>>>     record
>>>>        A : String (1 to Size);
>>>>     end record MyRecType;
>>>
>>> Isn't this a little bit overkill given that it is already possible
>>> to have unbounded arrays as record elements ?
>>
>> Not if you want to do something like:
>>
>> entity MyEntity is
>>     generic(
>>        Size : Natural := 10
>>     );
>>     port(
>>        IP : in  MyRecType generic map(Size);
>>        OP : out MyRecType generic map(Size)
>>     );
>> end entity MyEntity;
>>
>> You could decompose the records at the port, but with bigger record
>> structures this will become very cumbersome.
>
> My point is that this overlaps record_constraint.  What would be the syntax if
> you have both ?  Would that be readable ?
>
> Beside the syntax, the semantic is not clear to me.  When you 'instantiate' a
> type, is it a new type or a subtype ?
>
> The complexity becomes very high.
>
> What is wrong with:
>
> type MyRecType is record
>    A : String;
> end record;
>
> entity MyEntity is
>    port (IP : in MyRecType;
>          OP : out MyRecType);
> end MyEntity;

The string remains unconstrained.

> [ In Ada, the discriminants is either a discrete type or an access type.  I
> suppose vhdl is not interested in access type here.  But setting the
> discriminant doesn't create a new type.  Furthermore it is possible to change
> the discriminant(s) under some restrictions. ]

I think the syntax can accommodate both semantics:


    type BitRecType is
       generic(
          Size : Natural
       );
       record
          A : String (1 to Size);
          B : Std_Logic_Vector;
       end record BitRecType;

    entity BitEntity is
       generic(
          Size  : Natural := 10;
          Width : Natural := 8
       );
       port(
          IP : in  BitRecType( B(Width - 1 downto 0) ) generic map(Size);
          OP : out BitRecType( B(Width - 1 downto 0) ) generic map(Size)
       );
    end entity BitEntity;


I think that the 'record_constraint' is syntactically differentiated


-- 

Regards,

         Brent Hayhoe.