Re: [vhdl-200x] interface proposals

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[...]
> I think the syntax can accommodate both semantics:
> 
> 
>     type BitRecType is
>        generic(
>           Size : Natural
>        );
>        record
>           A : String (1 to Size);
>           B : Std_Logic_Vector;
>        end record BitRecType;
> 
>     entity BitEntity is
>        generic(
>           Size  : Natural := 10;
>           Width : Natural := 8
>        );
>        port(
>           IP : in  BitRecType( B(Width - 1 downto 0) ) generic
>           map(Size);
>           OP : out BitRecType( B(Width - 1 downto 0) ) generic
>           map(Size)
>        );
>     end entity BitEntity;
> 
> 
> I think that the 'record_constraint' is syntactically differentiated

The fact that there is two possible ways ('generic' and unconstrained
elements) for the same higher level feature (specifying the size of
elements) is not a good sign.

You haven't answered my first question: is an 'instance' of a type
with a generic part a new type or the same type ?

Tristan.