Re: [vhdl-200x] interface proposals

Some thoughts:

-- So this is the Ada 'discriminated record' type that I presume we are
-- discussing. The way it looks to me is just a 'constant generic' applied to -- 
the record type:

type Discriminated_Record (Size : Natural) is
    record
       A : String (1 .. Size);
    end record;

-- So if I VHDL'asize this we could have a generic block preceding the record
-- block in the type declaration.

-- We then need to 'generic map' the 'Size' value through when we declare a
-- constant and signals:

type MyRecType is
    generic(
       Size : Natural
    );
    record
       A : String (1 to Size);
    end record MyRecType;

constant MyRecConst  : MyRecType generic map(10) := (A => "0123456789AB");

signal   MyRecSig1   : MyRecType generic map(10) := MyRecConst;

signal   MyRecSig2   : MyRecType generic map(Size => 10);


-- Bearing in mind the ability to have a arrays of records, we need to be able
-- to apply generics to arrays in a similar manner.

-- Now in the type declaration we need to pass the generic through to the
-- record elements using a generic map construct:

type MyArryType is
    generic(
       Size : Natural
    );
    array(1 to 20) of
       MyRecType generic map(Size);

constant MyArryConst : MyArryType generic map(10) :=
                                        (1 to 20 => (A => "0123456789AB"));

signal   MyArrySig1  : MyArryType generic map(10) := MyRecConst;

signal   MyArrySig2  : MyArryType generic map(Size => 10);


-- The syntax suggested above is meant to be similar to that of entities with
-- generics and the mapping of the generics done at an equivalent instantiation
-- point.

-- The alternative is to instantiate similar to packages or maybe we allow both
-- optional forms?

-- Let's assume 'MyRecType' is declared in a package somewhere. We instantiate
-- it as shown:

type MyRecType_10 is new MyRecType
    generic map(Size => 10);

constant MyRecConst  : MyRecType_10 := (A => "0123456789AB");

signal   MyRecSig1   : MyRecType_10 := MyRecConst;

signal   MyRecSig2   : MyRecType_10;

-- For the array we may want to now define it as:

type MyArryType_10 is
    array(1 to 20) of
       MyRecType_10;

-- This is fine unless we want to keep the generic nature of the array type and
-- declare it within the package. In this case we need to to use the first
-- embedded 'generic map' syntax within the array declaration syntax.

-- Maybe we should allow both?

Regards,

Brent.


On 19/11/2015 22:05, Jason Borland wrote:
> That would work very well.
>
> Jason
>
> Sent from my iPhone
>
>> On 19 Nov 2015, at 9:12 p.m., Jim Lewis <Jim@synthworks.com> wrote:
>>
>> Hi,
>> In this weeks meeting some expressed concerns about generics on interfaces.
>>
>> ADA has a concept of discriminants that actually may address the situation we
>> are working with well.  See the web page:
>> https://en.wikibooks.org/wiki/Ada_Programming/Types/record
>>
>> Cheers,
>> Jim
>>
>> --
>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> Jim Lewis
>> VHDL Training Expert, SynthWorks
>> IEEE 1076 VHDL Working Group Chair
>> Open Source VHDL Verification Methodology (OSVVM), Chief Architect and Co-founder
>>
>> 1-503-590-4787
>> Jim@SynthWorks.com
>> http://www.SynthWorks.com
>>
>> VHDL Training on leading-edge, best coding practices for hardware design and verification.
>> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~