Re: [vhdl-200x] What is Minimal Risk?

I would aim for source compatibility, add new features but all existing
code should compile without any modification.

In practice that would mean:

   - Don't change existing types and subprograms
   - Don't introduce new keywords
   - Don't add overloaded subprograms if they can introduce ambiguities

I'm not sure if your example is valid Jim.

'0' & A + '0' & B is always parsed as ((('0' & A) + '0') & B)

It compiles in 2008 but it will not work in practice because the resulting
vector has the wrong size, this is caused by the order of operations.

With a 93 compiler you example doesn't work because "+"(unsigned,
std_ulogic) doesn't exist. So I'm not really sure what you mean here.
But I can see how a new overload can make certain expressions ambiguous..


2015-04-28 18:10 GMT+02:00 Degroat, Joanne <degroat.1@osu.edu>:

> I agree that we don't break old code.
>
> In the case of having to use parens below I don’t see a real problem.
> There should be an explanation, similar to the words in this email, in the
> standard on this.
>
> Joanne
>
> -----Original Message-----
> From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf
> Of Jim Lewis
> Sent: Tuesday, April 28, 2015 11:47 AM
> To: vhdl-200x@eda.org
> Subject: [vhdl-200x] What is Minimal Risk?
>
> Hi All,
> Martin raised an interesting issue, what is "minimal risk".   Any comments?
>
>  From my perspective, one big issue is that we don't accidentally break
> old code.
> For example, in VHDL-2008, the standard packages now includes the function:
> function "+"(L: unsigned, R: std_ulogic) return unsigned ;
>
> Unfortunately this means that old code of the form will result in an error
> since & and + have equal precedence and evaluate left to right:
> signal A, B : unsigned (7 downto 0) ;
> signal Y : unsigned(8 downto 0) ;
> Y <= '0' & A + '0' & B ;
>
> With parentheses added the code is fine:
> Y <= '0' & A + ('0' & B) ;
>
> Since most tools allow specification of a compile switch, so this issue is
> not challenging to work around.
>
> Best Regards,
> Jim
>
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis                                  Jim@SynthWorks.com
> VHDL Training Expert                       http://www.SynthWorks.com
> IEEE VHDL Working Group Chair
> OSVVM, Chief Architect and Cofounder
> 1-503-590-4787
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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