RE: [vhdl-200x] What is Minimal Risk?

I agree that we don't break old code.

In the case of having to use parens below I don’t see a real problem.
There should be an explanation, similar to the words in this email, in the standard on this.

Joanne

-----Original Message-----
From: owner-vhdl-200x@eda.org [mailto:owner-vhdl-200x@eda.org] On Behalf Of Jim Lewis
Sent: Tuesday, April 28, 2015 11:47 AM
To: vhdl-200x@eda.org
Subject: [vhdl-200x] What is Minimal Risk?

Hi All,
Martin raised an interesting issue, what is "minimal risk".   Any comments?

 From my perspective, one big issue is that we don't accidentally break old code.
For example, in VHDL-2008, the standard packages now includes the function:
function "+"(L: unsigned, R: std_ulogic) return unsigned ;

Unfortunately this means that old code of the form will result in an error since & and + have equal precedence and evaluate left to right:
signal A, B : unsigned (7 downto 0) ;
signal Y : unsigned(8 downto 0) ;
Y <= '0' & A + '0' & B ;

With parentheses added the code is fine:
Y <= '0' & A + ('0' & B) ;

Since most tools allow specification of a compile switch, so this issue is not challenging to work around.

Best Regards,
Jim

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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis                                  Jim@SynthWorks.com
VHDL Training Expert                       http://www.SynthWorks.com
IEEE VHDL Working Group Chair
OSVVM, Chief Architect and Cofounder
1-503-590-4787
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