Re: [vhdl-200x] Standard Package enhancements

On 04/16/2015 08:06 AM, Daniel Kho wrote:
> Hi all,
> There are a few enhancements I would like to propose for some of our 
> standard packages. Do let me know what you think.
>
> standard.vhd:
>     type BOOLEAN_VECTOR is array (INTEGER range <>) of BOOLEAN;
>     type BIT_VECTOR is array (INTEGER range <>) of BIT;
>     type INTEGER_VECTOR is array (INTEGER range <>) of INTEGER;
>     type REAL_VECTOR is array (INTEGER range <>) of REAL;
>     type TIME_VECTOR is array (INTEGER range <>) of TIME;
>
> Propose to change the ranges from (natural range <>) to (integer range 
> <>). I notice that quite often I have to change my types to 
> std_ulogic* types because the ranges can't be made negative. Just to 
> give you an example. I have a signal declared like this (it's a bundle 
> of flags which gets outputted from some computational operation):
>     flags: out boolean_vector(-8 to 8);
>

Compatibility problem here.   What if I do:

xxx : integer_vector (0 to 3) := (0,1,2,3);
Then say:
if (xxx = (0,1,2,3)) then
.....

(0,1,2,3) will assume to be integer'low to integer'low+4.


If std_logic_vector you can do:
xxx = "000" because 'low is zero.

I have special traps written to find cases like this in the fixed and 
floating point packages.


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